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MC10E1652FNG

P1-P3P4-P6P7-P9
MC10E1652
http://onsemi.com
4
Figure 3. Typical Hysteresis Curve Figure 4. Hysteresis Programming Voltage
40
30
20
10
0
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-20 -16 -12 -8 -4 Vref 4 8 12 16 20 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Vin, DIFFERENTIAL INPUT VOLTAGE (mV) PROGRAMMING VOLTAGE (VOLTAGE ABOVE VEE)
Q, OUTPUT VOLTAGE (V)
HYSTERESIS, (mV)
HYSTERESIS
T = 0°C
T =
85°C
T =
25°C
Table 5. AC CHARACTERISTICS V
CC
= +5.0 V ±5%; V
EE
= −5.2 V ±5%, V
CC
= 0 V (Note 6)
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle Frequency TBD > 1.0 TBD GHz
t
PLH
t
PHL
Propagation Delay to Output (Note 7)
V to Q
LEN
to Q
750
550
900
725
1050
900
775
550
925
750
1075
900
850
650
1025
825
1200
1000
ps
t
s
Setup Time
V
450 300 450 300 550 350
ps
t
h
Enable Hold Time
V
−50 −250 −50 −250 −100 −250
ps
t
pw
Minimum Pulse Width
LEN
400 400 400
ps
t
skew
Within Device Skew (Note 8) 15 15 15 ps
t
JITTER
Cycle−to−Cycle Jitter TBD TBD TBD ps
T
DE
Delay Dispersion
(ECL Levels) (Notes 9 10)
(Notes 9, 11)
100
60
ps
T
DL
Delay Dispersion
(TTL Levels) (Notes 12, 13)
(Notes 11, 12)
350
100
ps
VPP Differential Input Voltage |V1 − V2| 3.7 3.7 3.7 V
t
r
t
f
Rise/Fall Times
(20-80%)
225 325 475 225 325 475 250 375 500
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input V
IL
and V
IH
parameters vary 1:1 with V
CC
. Output V
OH
and V
OL
parameters vary 1:1 with GND.
7. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q
output
signals. For propagation delay measurements the threshold level (V
THR
) is centered about an 850 mV input logic swing with a slew rate of
0.75 V/NS. There is an insignificant change in the propagation delay over the input common mode range.
8. t
skew
is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.
9. Refer to Figure 4 and note that the input is at 850 mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q
output signals.
10.The slew rate is 0.25 V/NS for input rising edges.
11. The slew rate is 0.75 V/NS for input rising edges.
12.Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q
output signals.
13.The slew rate is 0.3 V/NS for input rising edges.
MC10E1652
http://onsemi.com
5
APPLICATIONS INFORMATION
The timing diagram (Figure 5.) is presented to illustrate
the MC10E1652’s compare and latch features. When the
signal on the LEN
pin is at a logic high level, the device is
operating in the “compare mode,” and the signal on the input
arrives at the output after a nominal propagation delay (t
PHL
,
t
PLH
). The input signal must be asserted for a time, t
s
, prior
to the negative going transition on LEN
and held for a time,
t
h
, after the LEN transition. After time t
h
, the latch is
operating in the “latch mode,” thus transitions on the input
do not appear at the output. The device continues to operate
in the “latch mode” until the latch is asserted once again.
Moreover, the LEN
pulse must meet the minimum pulse
width (t
pw
) requirement to effect the correct input-output
relationship. Note that the LEN
waveform in Figure 5.
shows the LEN
signal swinging around a reference labeled
VBB
INT
; this waveform emphasizes the requirement that
LEN
follow typical ECL 10KH logic levels because
VBB
INT
is the internally generated reference level, hence is
nominally at the ECL VBB level.
Finally, V
OD
is the input voltage overdrive and represents
the voltage level beyond the threshold level (V
THR
) to which
the input is driven. As an example, if the threshold level is
set on one of the comparator inputs as 80 mV and the input
signal swing on the complementary input is from zero to 100
mV, the positive going overdrive would be 20 mV and the
negative going overdrive would be 80 mV. The result of
differing overdrive levels is that the devices have shorter
propagation delays with greater overdrive because the
threshold level is crossed sooner than the case of lower
overdrive levels. Typically, semiconductor manufactures
refer to the threshold voltage as the input offset voltage
(VOS) since the threshold voltage is the sum of the
externally supplied reference voltage and inherent device
offset voltage.
Figure 5. Input/Output Timing Diagram
Q
Q
V
THR
V
LEN
VBB
INT
V
OD
t
pw
t
h
t
s
t
PHL
t
PLH(LEN)
V
IN
MC10E1652
http://onsemi.com
6
DELAY DISPERSION
Under a constant set of input conditions comparators have
a specified nominal propagation delay. However, since
propagation delay is a function of input slew rate and input
voltage overdrive the delay dispersion parameters, T
DE
and
T
DT
, are provided to allow the user to adjust for these
variables (where T
DE
and T
DT
apply to inputs with standard
ECL and TTL levels, respectively).
Figure 6. and Figure 7. define a range of input conditions
which incorporate varying input slew rates and input voltage
overdrive. For input parameters that adhere to these
constraints the propagation delay can be described as:
T
NOM
± T
DE
(or T
DT
)
where T
NOM
is the nominal propagation delay. T
NOM
accounts for nonuniformity introduced by temperature and
voltage variability, whereas the delay dispersion parameter
takes into consideration input slew rate and input voltage
overdrive variability. Thus a modified propagation delay can
be approximated to account for the effects of input conditions
that differ from those under which the parts where tested. For
example, an application may specify an ECL input with a
slew rate of 0.25 V/NS, an overdrive of 17 mV and a
temperature of 25°C, the delay dispersion parameter would
be 100 ps. The modified propagation delay would be
775 ps ± 100 ps
Figure 6. ECL Dispersion Test Input Conditions Figure 7. TTL Dispersion Test Input Conditions
0 V
0.5 V
2.0 V
2.5 V
- 1.75 V
- 1.58 V
- 1.07 V
-0.9 V
SLEW RATE = 0.75 V/NS
SLEW RATE = 0.75 V/NS
SLEW RATE =
0.25 V/NS
SLEW RATE =
0.30 V/NS
INPUT
THRESHOLD
RANGE
INPUT
THRESHOLD
RANGE
P1-P3P4-P6P7-P9

MC10E1652FNG

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Buy MC10E1652FNG
Manufacturer:
ON Semiconductor
Description:
Analog Comparators 5V ECL Dual ECL Output Comparato
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