1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
MAY 2010
2003 Integrated Device Technology, Inc. DSC 6394/10c
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin is used to synchronize the outputs
to the clock input
Output Skew <200 ps
Low jitter <200 ps cycle-to-cycle
1x, 2x, 4x output options (see table):
IDT23S08-1 1x
IDT23S08-2 1x, 2x
IDT23S08-3 2x, 4x
IDT23S08-4 2x
IDT23S08-1H, -2H, and -5H for High Drive
No external RC network required
Operates at 3.3V VDD
Spread spectrum compatible
Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT23S08 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08 enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT23S08 is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08 is characterized for both Industrial and Commercial opera-
tion.
IDT23S08
3.3V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
PLL
S1
2
14
15
3
CLKA1
CLKA2
CLKA3
CLKA4
6
10
11
CLKB1
CLKB2
CLKB3
CLKB4
9
FBK
16
Control
Logic
7
8
1
REF
S2
(-2, -3)
(-3, -4)
(-5)
2
2
2
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
PIN CONFIGURATION
SOIC/ TSSOP
TOP VIEW
REF
CLKA1
S2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
161
CLKA2
GND
CLKB1
FBK
CLKA4
GND
S1
V
DD
VDD
CLKB2
CLKB3
CLKB4
CLKA3
Symbol Rating Max. Unit
VDD Supply Voltage Range –0.5 to +4.6 V
VI
(2)
Input Voltage Range (REF) –0.5 to +5.5 V
V
I Input Voltage Range –0.5 to V
(except REF) VDD+0.5
IIK (VI < 0) Input Clamp Current 50 mA
IO Continuous Output Current ±50 mA
(VO = 0 to VDD)
VDD or GND Continuous Current ±100 mA
TA = 55°C Maximum Power Dissipation 0.7 W
(in still air)
(3)
TSTG Storage Temperature Range –65 to +150 ° C
Operating Commercial Temperature 0 to +70 °C
Temperature Range
Operating Industrial Temperature -40 to +85 °C
Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Pin Number Functional Description
REF
(1)
1 Input Reference Clock, 5 Volt Tolerant Input
CLKA1
(2)
2 Clock Output for Bank A
CLKA2
(2)
3 Clock Output for Bank A
VDD 4 3.3V Supply
GND 5 Ground
CLKB1
(2)
6 Clock Output for Bank B
CLKB2
(2)
7 Clock Output for Bank B
S2
(3)
8 Select Input, Bit 2
S1
(3)
9 Select Input, Bit 1
CLKB3
(2)
10 Clock Output for Bank B
CLKB4
(2)
11 Clock Output for Bank B
GND 12 Ground
VDD 13 3.3V Supply
CLKA3
(2)
14 Clock Output for Bank A
CLKA4
(2)
15 Clock Output for Bank A
FBK 16 PLL Feedback Input
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
(1)
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
Device Feedback From Bank A Frequency Bank B Frequency
IDT23S08-1 Bank A or Bank B Reference Reference
IDT23S08-1H Bank A or Bank B Reference Reference
IDT23S08-2 Bank A Reference Reference/2
IDT23S08-2 Bank B 2 x Reference Reference
IDT23S08-2H
(1)
Bank A Reference Reference/2
IDT23S08-2H
(1)
Bank B 2 x Reference Reference
IDT23S08-3
(1)
Bank A 2 x Reference Reference or Reference
(2)
IDT23S08-3
(1)
Bank B 4 x Reference 2 x Reference
IDT23S08-4 Bank A or Bank B 2 x Reference 2 x Reference
IDT23S08-5H Bank A or Bank B Reference/2 Reference/2
NOTES:
1. Contact factory for availability.
2. Output phase is indeterminant (0° or 180° from input clock).
AVAILABLE OPTIONS FOR IDT23S08
S2 S1 CLK A CLK B Output Source PLL Shut Down
L L Tri-State Tri-State PLL Y
L H Driven Tri-State PLL N
H L Driven Driven REF Y
H H Driven Driven PLL N
FUNCTION TABLE
(1)
SELECT INPUT DECODING
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.

23S08-1DCG

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 3.3V CLOCK BUFFER SPREAD SPECTRUM
Lifecycle:
New from this manufacturer.
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