ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT™ / ICS™
SERIALLY PROGRAMMABLE CLOCK SOURCE 7
ICS307-03 REV H 071708
Table 8. Miscellaneous Control Bits
External Components
The ICS307-03 requires a minimum number of external components for proper operation.
Decoupling Capacitors
TheICS307-03 requires 0.01µF decoupling capacitors to be connected between each VDD pin and the Ground Plane. The
0.01µF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead inductance.
Output Termination
The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation with single
ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50 Ohm transmission
line without the need for any series resistors.
Crystal Selection
A parallel resonant, fundamental mode crystal with a load
(correlation) capacitance of 12 pF should be used. For
crystals with a specified load capacitance greater than 12
pF, additional crystal capacitors may be connected from
each of the pins X1 and X2 to ground as shown in the Block
Diagram on page 1. The value (in pF) of these crystal caps
should be = (C
L
-12)*2, where C
L
is the crystal load
capacitance in pF.
For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.
Initial Output Frequency
ICS307-03 on-chip registers are initially configured to
provide a 1x output clock on the CLK1 output, and 0.5x clock
on CLK2 and CLK3. The output frequency will be the same
as the input clock or crystal for input frequencies from 10 -
50 MHz. This is useful when the ICS307-03 needs to
provide an initial system clock at power-up.
Bit Function
24~88 Reserved—set to 0
110 OE1—set to 1 to enable CLK1
111 OE2—set to 1 to enable CLK2
112 1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO
122 Crystal Input = 1, Clock Input = 0
123 Selects source for CLK2 (see block diagram)
124 Selects source for CLK3 (see block diagram)
125 Reserved—set to 0
126 Reserved—set to 0
129 OE3—set to 1 to enable CLK3
130 Reserved—set to 0
131 Reserved—set to 0
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT™ / ICS™
SERIALLY PROGRAMMABLE CLOCK SOURCE 8
ICS307-03 REV H 071708
Determining and Controlling the Output Frequency with VersaClock
TM
II
The ICS307-03 is directly supported by the IDT provided
software called VersaClock II. Complete programming
words for this device can be calculated on any Windows PC
by running the VersaClock II software and simple inputting
desired input and output frequencies. Once the software
generates an appropriate programming word, it may then be
either copied to the Windows clipboard or even directly
programmed into the ICS307-03 via the host computers
parallel port.
For more information on VersaClock II, please visit
www.icst.com or send an e-mail to ics-mk@icst.com.
Manually Determining the Output Frequency
The user has full control over the desired output frequency
as long as it is operated within the limits shown in the AC
Electrical Characteristics.
The output of the ICS307-03 can be determined by the
following equation:
Where:
VCO Divider (V) = 12 to 2055
Reference Divider Word (R) = 1 to 2055
Output Divider = values in tables 5, 6, 7
Also, the following operating ranges should be observed.
To determine the best combination of VCO, reference, and
output dividers, please use the VersaClock II software
mentioned above.
Default Register Values
At power-up, the registers are set to:
ref divide = 5
VCO divide = 50
output divide = 10 (CLK1)
output divide = 2 (CLK2)
output divide = 2 (CLK3)
bit 123, 124 = 1
ICP = 3.75 µA
R = 16k
Default programming word is:
0x31FFDFFEE3BFFFFFFFFFFFFFFFF055FF2
C
LK1Frequency InputFrequency
V
RO
D
------------------
--
=
V
COmin InputFrequency
V
R
---- VCOmaxfre
q
<<
20kHz
Input Frequency
R
-------------------------------------------100MHz<<
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT™ / ICS™
SERIALLY PROGRAMMABLE CLOCK SOURCE 9
ICS307-03 REV H 071708
Programming Interface
The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time after
power is properly applied. If V or R values are changed, the frequency will transition smoothly to the new value
without glitches or short cycles. However, changing any divider or mux in the output signal path may generate a
glitch.
The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data bit value in
the rising edge. It latches the most recently shifted 132 bit values into the control register of device whenever CS is
high. Care must be taken to ensure that CS is always low until the system is ready to load in a new register value
and that SCLK is never toggled high when CS is high.
The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit 112 held
low) with the waveform and timing shown below:.
Figure 2: ICS307-03 Programming Timing Diagram
Table 8: AC Parameters for Programming the ICS307-03
Programming with VersaClock Software
The VersaClock II Software not only generates the programming word for the user, it can also be used to program the device
via the host computer’s parallel port. Demonstration boards are available from IDT that allows the VersaClock II S/W to
directly connect the ICS307-03 to a Windows based PC’s DB-25 parallel port connector and programmed simply by pressing
the “Program Part” button.
Parameter Condition Min. Max. Units
t
SETUP
Setup time 2.5 ns
t
HOLD
Hold time after SCLK 2.5 ns
t
W
Data wait time 2.5 ns
t
S
Strobe pulse width 10 ns
SCLK Frequency 200 MHz
128129130131 10
t
hold
t
setup
2
SCLK
CS
t
s
t
w
DIN

ICS307G-03T

Mfr. #:
Manufacturer:
Description:
IC SRL PROGR CLK SOURCE 16-TSSOP
Lifecycle:
New from this manufacturer.
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