FMS6246 Rev. 1B 7 www.fairchildsemi.com
FMS6246 Six Channel, 6th Order SD/PS Video Filter Driver
The same method can be used for biased signals with the addi-
tion of a pull-up resistor to make sure the clamp never operates.
The internal pull-down resistance is 800kΩ ±20% so the exter-
nal resistance should be 7.5MΩ to set the DC level to 500mV. If
a pull-up resistance less than 7.5MΩ is desired, an external
pull-down can be added such that the DC input level is set to
500mV.
Figure 14. Biased SCART with DC-coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired.
Figure 15. DC-coupled Inputs, AC-coupled Outputs
Figure 16. AC-coupled Inputs, AC-coupled Outputs
Figure 17. Biased SCART with AC-coupled Outputs
NOTE: The video tilt or line time distortion will be dominated by
the AC-coupling capacitor. The value may need to be increased
beyond 220µF in order to obtain satisfactory operation in some
applications.
Power Dissipation
The FMS6246 output drive configuration must be considered
when calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature. The fol-
lowing example can be used to calculate the FMS6246’s power
dissipation and internal temperature rise.
T
j
= T
A
+ P
d
• Θ
JA
where P
d
= P
CH1
+ P
CH2
+ P
CHx
and P
CHx
= V
s
• I
CH
- (V
O
2
/R
L
)
where
V
O
= 2V
in
+ 0.280V
I
CH
= (I
CC
/ 6) + (V
O
/R
L
)
V
in
= RMS value of input signal
I
CC
= 60mA
V
s
= 5V
R
L
= channel load resistance
Board layout can also affect thermal characteristics. Refer to the
Layout Considerations Section for more information.
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6246DEMO, to use as a
guide for layout and to aid in device testing and characteriza-
tion. The FMS6246DEMO is a 4-layer board with a full power
and ground plane. Following this layout configuration will pro-
vide the optimum performance and thermal characteristics. For
optimum results, follow the steps below as a basis for high fre-
quency layout:
• Include 10µF and 0.1µF ceramic bypass capacitors
• Place the 10µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
•For multi-layer boards, use a large ground plane to help dissi-
pate heat
•For 2 layer boards, use a ground plane that extends beyond
the device by at least 0.5”
• Minimize all trace lengths to reduce series inductances
LCVF
Bias
Input
0.1u
External Video
source must
be AC-coupled.
500mV +/-350mV
75Ω
7.5MΩ
75Ω
DVD or
STB
SoC
DAC
Output
75Ω
LCVF
Clamp
Inactive
0V - 1.4V
220u
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1u
0V - 1.4V
75Ω
220μ
LCVF
Clamp
Active
0.1μ
External video
source must
be AC-coupled.
500mV +/-350mV
220μ
75Ω
7.5MΩ
75Ω
