MK1574-01BSILFTR

MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL 7
MK1574-01A/B REV D 051310
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of
the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is
recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or
NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric
properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is
converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are
calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set
by the capacitor C and the constant K1 using the formula:
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page 7)
shows the constants K1 = 0.0516 and K2 = 6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using equation 1,
Therefore,
3. A good value for the damping factor ζ is 0.707. From equation 2,
BW (Hz) =
C
K1
Equation 1
R =
Equation 2; ζ (zeta) is the damping factor
C
ζ * K2
C
K1
400 =
C
K1
C =
400
0.0516
(
)
2
= 16.6 nF (16 nF nearest standard value
R =
= 34.7 k (36 k nearest standard value)
16E-9
0.707 * 6.2
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL 8
MK1574-01A/B REV D 051310
Loop Filter Constants
This table shows the constants K1 and K2 that are used with the equations on page 6 to calculate the external loop filter
components.Loop Filter Contstants for MK1574-01A
PC Board Layout
A proper board layout is critical to the successful use of the MK1574-01A/B. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP1 at pin 4 is the most sensitive). Traces must be as short as possible
and the capacitor and resistor must be mounted next to the device as shown to the right. The capacitor connected
between pins 3 and 5 is the power supply decoupling capacitor. The high frequency output clocks on may benefit
from a series 33 resistor connected close to the pin (not shown).
Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1574-01A/B ROM, which yield the exact values
shown for the output clocks.
Decode Address Loop Filter Constants
FS3:0 (Hex) K1 K2
0000 0 Reserved Reserved
0001 1 Reserved Reserved
0010 2 Reserved Reserved
0011 3 Reserved Reserved
0100 4 0.0430 7.4
0101 5 0.0527 6.0
0110 6 0.0444 7.2
0111 7 0.0454 7.0
1000 8 0.0533 6.0
1001 9 0.0410 7.8
1010 A 0.0508 6.3
1011 B 0.0587 5.4
1100 C 0.0365 8.7
1101 D 0.0420 7.6
1110 E 0.0516 6.2
1111 F 0.0594 5.4
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
FRAME RATE COMMUNICATIONS PLL 9
MK1574-01A/B REV D 051310
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
16
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004)
C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.330.51.013.020
C 0.19 0.25 .0075 .0098
D 9.80 10.00 .3859 .3937
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.250.50.010.020
L 0.401.27.016.050
α 0° 8° 0° 8°

MK1574-01BSILFTR

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner FRAME RATE COMMUNICATION PLL
Lifecycle:
New from this manufacturer.
Delivery:
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