LTC6416
11
6416f
PIN FUNCTIONS
V
CM
(Pin 1): This pin sets the output common mode voltage
seen at OUT
+
and OUT
–
by driving IN
+
and IN
–
through an
internal buffer with a high output resistance of 6k. The V
CM
pin has a Thevenin equivalent resistance of approximately
3.8k and can be overdriven by an external voltage. If no
voltage is applied to V
CM
, it will fl oat to a default voltage
of approximately 1.25V on a 3.3V supply or 1.36V on
a 3.6V supply. The V
CM
pin should be bypassed with a
high-quality ceramic bypass capacitor of at least 0.1µF.
CLHI (Pin 2): High Side Clamp Voltage. The voltage applied
to the CLHI pin defi nes the upper voltage limit of the OUT
+
and OUT
–
pins. This voltage should be set at least 300mV
above the upper voltage range of the driven ADC. On a 3.3V
supply, the CLHI pin will fl oat to a 2.23V default voltage.
On a 3.6V supply, the CLHI pin will fl oat to a 2.45V default
voltage. CLHI has a Thevenin equivalent of approximately
4.1k and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high-quality ceramic
bypass capacitor of at least 0.1µF.
IN
+
,IN
–
(Pins 3, 4): Non-inverting and inverting input pins
of the buffer, respectively. These pins are high impedance,
approximately 6k. If AC-coupled, these pins will self bias
to the voltage present at the V
CM
pin.
CLLO (Pin 5): Low Side Clamp Voltage. The voltage ap-
plied to the CLLO pin defi nes the lower voltage limit of
the OUT
+
and OUT
–
pins. This voltage should be set at
least 300mV below the lower voltage range of the driven
ADC. On a 3.3V supply, the CLLO pin will fl oat to a 0.25V
default voltage. On a 3.6V supply, the CLLO pin will fl oat to
a 0.265V default voltage. CLLO has a Thevenin equivalent
resistance of approximately 2.3k and can be overdriven by
an external voltage. The CLLO pin should be bypassed with
a high quality ceramic bypass capacitor of at least 0.1µF.
GND (Pins 6, 9, 11): Negative power supply, normally
tied to ground. Both pins and the exposed paddle must
be tied to the same voltage. GND may be tied to a voltage
other than ground as long as the voltage between V
+
and
GND is 2.7V to 4V. If the GND pins are not tied to ground,
bypass them with 680pF and 0.1µF capacitors as close to
the package as possible.
OUT
–
, OUT
+
(Pins 7, 8): Outputs. The LTC6416 outputs
are low impedance. Each output has an output impedance
of approximately 9 at DC.
V
+
(Pin 10): Positive Power Supply. Typically 3.3V to 3.6V.
Split supplies are possible as long as the voltage between
V
+
and GND is 2.7V to 4V. Bypass capacitors of 680pF
and 0.1µF as close to the part as possible should be used
between the supplies.
Exposed Pad (Pin 11): Ground. The exposed pad must
be soldered to the printed circuit board ground plane for
good heat transfer. If GND is a voltage other than ground,
the Exposed Pad must be connected to a plane with the
same potential as the GND pins – Not to the system
ground plane.
DC TEST CIRCUIT SCHEMATIC
8
1
2
3
4
5
6
9
11
7
C
LOAD
V
+
V
+
10
OUT
–
6416 DC
OUT
+ OUT
–
OUT
+
R
LOAD
V
CM
V
CM
IN
+
IN
+
CLHICLHI
CLLOCLLO
IN
–
IN
–
LTC6416
V
INDIFF
= IN
+
– IN
–
IN
+
+ IN
–
2
V
INCM
=
V
OUTDIFF
= OUT
+
– OUT
–
OUT
+
+ OUT
–
2
V
OUTCM
=
