10
FN8093.5
December 4, 2015
Manual Reset
The manual reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR
input is an
active-low debounced input. By connecting a push-button
directly from MR
to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR
pin is pulled low to less than 100mV for 1µs or longer
while the push-button is closed. After MR
is released, the
reset outputs remain asserted for t
POR
(200ms) and then
released.
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t
WDT
(1.6s nominal),
otherwise the reset signal is asserted (see Figure 5).
Internally, the 1.6s timer is cleared by either a reset or by
toggling the WDI input.
Besides the 1.6s default timeout during normal operation,
these devices also have a longer 51s timeout for start-up.
During this time, a reset cannot be asserted due to the WDI
not being toggled. The longer delay at power-on allows an
operating system to boot, an FPGA to initialize, or the
system software to initialize without the burden of dealing
with the Watchdog.
Symbol Table
V
DD
RST/MR
PB
ISL88012
R
pu
ISL88013
ISL88014
ISL88015
ISL88011
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
FIGURE 5. WATCHDOG TIMING DIAGRAM
V
DD
WDI
RST
t
POR
V
THVDD
1V
STARTt
WDT
t
POR
t
WDT
>t
WDPS
<t
WDT
<t
WDT
START t
WDT
RST
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
