9
FN8093.5
December 4, 2015
Principles of Operation
The ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
devices provide those functions needed for critical voltage
monitoring. These features include Power-On Reset control,
customizable supply voltage supervision, Watchdog Timer
capability, and manual reset assertion. By integrating all of
these features into a small 5 Ld SOT-23 package and using
only 5.5µA of supply current, the ISL88011, ISL88012,
ISL88013, ISL88014, ISL88015 devices can assist in
lowering system cost, reducing board space requirements,
and increasing the reliability of a system.
Low Voltage Monitoring
During normal operation, these supervisors monitor both the
voltage level of V
DD
(ISL88011, ISL88012, ISL88013) and/or
VMON (ISL88012, ISL88014, ISL88015). The device asserts
a reset if any of these voltages falls below their respective
trip points. The reset signal effectively prevents the system
from operating during a power failure or brownout condition.
This reset signal remains asserted until V
DD
and the voltage
on VMON exceed their voltage threshold setting for the reset
time delay period t
POR
of 200ms (See Figure 1)
The ISL88012, ISL88014 and ISL88015 allow users to
customize the minimum voltage sense level on the VMON
input pin. To do this, connect an external resistor divider
network to the VMON pin in order to set the trip point to
some voltage above 600mV according to the following
Equation 1 (See Figure 2).
:
Power-On Reset (POR)
Applying at least 1V to the V
DD
pin activates a POR circuit
which asserts reset (i.e., RST
goes HIGH while RST goes
LOW). The reset signals remain asserted until the voltage at
V
DD
and/or VMON rise above the minimum voltage sense
level for time period t
POR
. This ensures that the voltages
have stabilized.
These reset signals provide several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
Adjusting POR Timeout via C
POR
Pin
On the ISL88011 and ISL88014, users can adjust the
Power-On Reset timeout delay (t
POR
) up to many times the
normal t
POR
of 250ms. To do this, connect a capacitor
between C
POR
and ground (see Figure 3). For example,
connecting a 30pF capacitor to C
POR
will increase t
POR
from a typical 250ms to about 2.5s. NOTE: Care should be
taken in PCB layout and capacitor placement in order to
reduce stray capacitance as much as possible, which
lengthens the t
POR
timeout period.
V
INTRIP
0.6
R
1
R
2
+
R
2
--------------------------
=
(EQ. 1)
ISL88012
V
IN
R
1
R
2
ISL88014
ISL88015
VMON
FIGURE 2. USING VMON TO MONITOR V
IN
VIA RESISTORS
0
2
3
5
0102030
C
POR
(pF)
t
POR
(s)
ISL88011
C
POR
ISL88014
FIGURE 3. ADJUSTING t
POR
WITH A CAPACITOR
40 50 60 70 80
4
1
6
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
