49FCT3805QG

4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
I
CC Quiescent Power Supply Current VCC = Max. 10 30 µA
TTL Inputs HIGH VIN = VCC –0.6V
(3)
ICCD Dynamic Power Supply Current
(4)
VCC = Max. VIN = VCC 0.035 0.06 mA/MHz
Outputs Open VIN = GND
OE
A = OEB = GND
Per Output Toggling
50% Duty Cycle
I
C Total Power Supply Current
(6)
VCC = Max. VIN = VCC 0.9 1.6
Outputs Open VIN = GND
f
O = 25MHz
50% Duty Cycle V
IN = VCC –0.6V 0.9 1.6
OEA = OEB = VCC VIN = GND
Mon. Output Toggling
VCC = Max. VIN = VCC —2033
(5)
mA
Outputs Open VIN = GND
fO = 50MHz
50% Duty Cycle VIN = VCC –0.6V 20 33
(5)
OEA = OEB = GND VIN = GND
Eleven Outputs Toggling
5
IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
(3,4)
FCT3805 FCT3805A
Symbol Parameter Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH Propagation Delay CL = 50pF 1.5 5.8 1.5 5.2 ns
tPHL INA to OAn, INB to OBn RL = 500
tR Output Rise Time 2 2 ns
tF Output Fall Time 2 2 ns
t
SK(O) Output skew: skew between outputs of all banks of 0.6 0.6 ns
same package (inputs tied together)
t
SK(P) Pulse skew: skew between opposite transitions 1 1 ns
of same output (|tPHL -– tPLH|)
tSK(T) Package skew: skew between outputs of different 1.5 1.2 ns
packages being driven by the same input source,
power supply voltage, temperature, frequency, and
speed grade.
t
PZL Output Enable Time 1.5 6.5 1.5 6 ns
tPZH OEA to OAn, OEB to OBn
t
PLZ Output Disable Time 1.5 5.5 1.5 5 ns
t
PHZ OEA to OAn, OEB to OBn
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - COMMERCIAL
(3,4)
FCT3805 FCT3805A
Symbol Parameter Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH Propagation Delay CL = 50pF 1.5 5.8 1.5 5 ns
tPHL INA to OAn, INB to OBn RL = 500
tR Output Rise Time 2 2 ns
tF Output Fall Time 2 2 ns
t
SK(O) Output skew: skew between outputs of all banks of 0.5 0.5 ns
same package (inputs tied together)
t
SK(P) Pulse skew: skew between opposite transitions 1 1 ns
of same output (|tPHL -– tPLH|)
t
SK(T) Package skew: skew between outputs of different 1.5 1.2 ns
packages being driven by the same input source,
power supply voltage, temperature, frequency, and
speed grade.
t
PZL Output Enable Time 1.5 6.5 1.5 6 ns
tPZH OEA to OAn, OEB to OBn
t
PLZ Output Disable Time 1.5 5.5 1.5 5 ns
t
PHZ OEA to OAn, OEB to OBn
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
D.U.T.
V
IN
V
OUT
V
CC
R
T
Pulse
Generator
50pF
500
500
6V
GND
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
0.3V
0.3V
t
PLZ
t
PZL
tPZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
3V
0V
VOH
tPLH tPHL
VOL
1.5V
1.5V
tR
tF
2.0V
0.8V
INPUT
OUTPUT
tPLH
tPHL
3V
0V
V
OH
1.5V
1.5V
V
OL
tSK(p) = |tPHL - tPLH|
INPUT
OUTPUT
tPLH1
OUTPUT 1
OUTPUT 2
tSK(o)
tPLH2
3V
0V
V
OH
1.5V
1.5V
V
OL
VOH
1.5V
V
OL
INPUT
tPHL1
tPHL2
tSK(o)
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
INPUT
tPLH1
PACKAGE 1
OUTPUT
t
SK(t)
tPLH2
3V
0V
V
OH
1.5V
1.5V
V
OL
VOH
1.5V
V
OL
tPHL1
tPHL2
tSK(t)
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
PACKAGE 2
OUTPUT
Package Delay
TEST CIRCUITS AND WAVEFORMS
Pulse Skew - tSK(P)
Test Circuits for All Outputs
DEFINITIONS:
C
L = Load capacitance: includes jig and probe capacitance.
R
T = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Switch
Disable LOW 6V
Enable LOW
Disable HIGH GND
Enable HIGH
SWITCH POSITION
Output Skew - tSK(X)
Output Skew - tSK(O)
Package Skew - tSK(T)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns

49FCT3805QG

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 3.3V Dual 1:5 Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
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