NCV7704, NCV7714
www.onsemi.com
31
STATUS_2 Register
Address: 12h
NCV7704:
Bit
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC − − R/RC R/RC − −
Bit name 0 0
OC
HS4
ULD
HS4
OC
HS5
ULD
HS5
OC
HS6
ULD
HS6
OC
HS7
ULD
HS7
0 0 VSUV VSOV 0 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NCV7714:
Bit
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC R/RC
Bit name 0 0
OC
HS4
ULD
HS4
OC
HS5
ULD
HS5
OC
HS6
ULD
HS6
OC
HS7
ULD
HS7
OC
ECFB
ULD
ECFB
VSUV VSOV ECLO ECHI
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUT4−7
Overcurrent
Detection
OCx Description Remark
0 No overcurrent detected
During an overcurrent event in one of the HS the belonging
overcurrent status bit STATUS_2.OCx is set and the dedicated
output is switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled, the output
will be reactivated automatically after a programmable delay
time (CONTROL_3.OCRF). If the overcurrent recovery bit is no
set the microcontroller has to clear the OC failure bit and to
reactivate the output stage again.
1 Overcurrent detected
OUT4−7
Underload
Detection
ULDx Description Remark
0 No underload detected
For each output stage an underload status bit ULD is available.
The underload detection is done in “on−mode”. If the load
current is below the undercurrent detection threshold for at
least td_uld, the corresponding underload bit ULDx is set.
If an ULD event occurs the global status bit ULD will be set.
It is possible to deactivate the global ULD failure bit by setting
the configuration bits CONFIG.NO_ULD_OUTn.
1 Underload detected
Vs
Undervoltage
VSUV Description Remark
0 No undervoltage detected
In case of an Vs undervoltage event, the output stages will be
deactivated immediately and the corresponding failure flag will
be set. By default the output stages will be reactivated
automatically after Vs is recovered unless the control bit
CONTROL_3.OVUVR is set. If this is the case (OVUVR=1) the
bit VSUV has to be cleared after an UV event.
1 Undervoltage detected
Vs
Overvoltage
VSOV Description Remark
0 No overvoltage detected
In case of an Vs overvoltage event, the output stages will be
deactivated immediately and the corresponding failure flag will
be set. By default the output stages will be reactivated
automatically after Vs is recovered unless the control bit
CONTROL_3.OVUVR is set. If this is the case (OVUVR=1) the
bit VSOV has to be cleared after an OV event.
1 Overvoltage detected
EC Mirror
Control
Status
ECLO ECHI Description Remark
0 0 ECM output regulation in range
Two comparators monitor the voltage at pin ECFB (feedback)
in electrocrome mode. If this voltage is below / above the
programmed target these bits signal the difference after at least
32 ms. The bits are not latched and may toggle after at least
32 ms, if the ECFB voltage has not yet reached the target. They
are not assigned to the Global Error Flag.
0 1 ECM output V > Vregulation
1 0 ECM output V < Vregulation
1 1 not used
