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MC74VHC257MELG

P1-P3P4-P6P7-P8
Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1 Publication Order Number:
MC74VHC257/D
MC74VHC257
Quad 2-Channel Multiplexer
with 3-State Outputs
The MC74VHC257 is an advanced high speed CMOS quad
2–channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2–input digital multiplexers with common select
(S) and enable (OE
) inputs. When (OE) is held High, selection of data
is inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The inputs tolerate voltages up to 7V, allowing the interface of 5V
systems to 3V systems.
• High Speed: t
PD
= 4.1ns (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 4µA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: FETs = 100; Equivalent Gates = 25
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S
Y0
B0
A0
Y1
B1
A1
GND
Y3
B3
A3
OE
V
CC
B2
A2
Y2
Figure 1. Pin Assignment
SO–16
http://onsemi.com
SO–16
D SUFFIX
CASE 751B
MARKING DIAGRAMS
1
8
9
16
1
8
16 9
VHC257
AWLYWW
VHC257
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
ORDERING INFORMATION
EIAJ SO–16
M SUFFIX
CASE 966
VHC257
ALYW
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
16
9
1
8
Device Package Shipping
MC74VHC257D SO–16 48 Units/Rail
MC74VHC257DT TSSOP–16 96 Units/Rail
MC74VHC257M EIAJ–SO–16 50 Units/Rail
MC74VHC257DR2 2500 Tape & Reel
MC74VHC257DTR2 TSSOP–16
2500 Tape & Reel
MC74VHC257MEL EIAJ–SO–16 2000 Tape & Reel
MC74VHC257
http://onsemi.com
2
Figure 2. Expanded Logic Diagram
4
7
9
12
2
3
5
6
11
10
14
13
15
1
A0
B0
A1
B1
A2
B2
A3
B3
Y0
Y1
Y2
Y3
OE
S
DATA
OUTPUTS
NIBBLE
INPUTS
OE S Y0 – Y3
A0 – A3, B0 – B3 = the levels
of the respective Data–Word
Inputs.
H
L
L
X
L
H
L
A0–A3
B0–B3
Inputs
Outputs
3
OE
S
A0
B0
A1
B1
A2
B2
2
5
6
11
10
14
13
12
9
7
4
Y0
MUX
Y1
Y2
Y3
EN
1
15
A3
B3
G1
1
1
Figure 3. IEC Logic Symbol
FUNCTION TABLE
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHC257
http://onsemi.com
3
MAXIMUM RATINGS (Note 1.)
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage –0.5 to +7.0 V
V
IN
Digital Input Voltage –0.5 to +7.0 V
V
OUT
DC Output Voltage –0.5 to V
CC
+0.5 V
I
IK
Input Diode Current –20 mA
I
OK
Output Diode Current 20 mA
I
OUT
DC Output Current, per Pin 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins 75 mA
P
D
Power Dissipation in Still Air SOIC Package
TSSOP
200
180
mW
T
STG
Storage Temperature Range –65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 2.)
Machine Model (Note 3.)
Charged Device Model (Note 4.)
>2000
>200
>2000
V
I
LATCH–UP
Latch–Up Performance Above V
CC
and Below GND at 125°C (Note 5.) 300 mA
JA
Thermal Resistance, Junction to Ambient SOIC Package
TSSOP
143
164
°C/W
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
DC Input Voltage 0 5.5 V
V
OUT
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature Range, all Package Types –55 125 °C
t
r
, t
f
Input Rise or Fall Time V
CC
= 3.3 V + 0.3 V
V
CC
= 5.0 V + 0.5 V
0 100
20
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
= 80
C°
T
J
= 90
C°
T
J
= 100 C°
T
J
= 110 C°
T
J
= 130 C°
T
J
= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 4. Failure Rate vs. Time Junction Temperature
P1-P3P4-P6P7-P8

MC74VHC257MELG

Mfr. #:
Buy MC74VHC257MELG
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 2-5.5V Quad 3-State 2-Channel
Lifecycle:
New from this manufacturer.
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