LTC2355-12/LTC2355-14
5
2355fb
For more information www.linear.com/LTC2355-12
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4: Offset and full-gain specifications are measured for a single-ended
A
IN
+
input with A
IN
–
grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between A
IN
+
and A
IN
–
.
Note 9: The absolute voltage at A
IN
+
and A
IN
–
must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3.3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Rate per Channel
(Conversion Rate)
l
3.5 MHz
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
l
286 ns
t
SCK
Clock Period (Note 16)
l
15.872 10000 ns
t
CONV
Conversion Time (Note 6) 17 18 SCLK cycles
t
1
Minimum High or Low SCLK Pulse Width (Note 6) 2 ns
t
2
CONV to SCK Setup Time (Notes 6, 10) 3 ns
t
3
Nearest SCK Edge Before CONV (Note 6) 0 ns
t
4
Minimum High or Low CONV Pulse Width (Note 6) 4 ns
t
5
SCK↑ to Sample Mode
(Note 6) 4 ns
t
6
CONV↑ to Hold Mode
(Notes 6, 11) 1.2 ns
t
7
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13) 45 ns
t
8
Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) 8 ns
t
9
SCK↑ to Hi-Z at SDO
(Notes 6, 12) 6 ns
t
10
Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t
12
V
REF
Settling Time After Sleep-to-Wake Transition (Note 14) 2 ms
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V
P-P
input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock.
Note 17: V
DD
= 3.3V, fSAMPLE = 3.5Msps.
Note 18: The LTC2355-14 is measured and specified with 14-bit resolution
(1LSB = 152µV) and the LTC2355-12 is measured and specified with
12-bit resolution (1LSB = 610µV).
Note 19: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
