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MN101LR05DXW

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MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
Publication date: October 2014 1
PubNo. 21705-019E
1.1 Product Summary
This LSI user's manual describes MN101LR05D/04D/03D/02D.
The detail of product specification is described mainly about MN101LR05D.
For the difference between each product, See [1.3 Comparison of Product Specification] and [1.4.1 Pin Configu-
ration].
V
DD18
voltage after reset release, oscillation stabilization wait time after reset release and ROM capacity vary
depending on the ROM name of each product. Table: 1.1.1 shows the difference of specifications between the
ROM name.
Table:1.1.1 Product Summary
..
When using the debugger or programmer, set "Product name + ROM name"
(e.g.: MN101LR05DXA/XW) in the field "Product type" or "Microcomputer product type".
When "ROM name" is set incorrectly, connect error is occurred.
When nothing is set to "ROM name", XA/XW is selected.
(e.g.: MN101LR05D MN101LR05DXA/XW)
..
Product Name ROM name * V
DD18
voltage after
reset release
Oscillation stabiliza-
tion wait time after
reset release
ROM (ReRAM) capacity
(Program area/Data area)
MN101LR05D
MN101LR04D
MN101LR03D
MN101LR02D
XW 1.1 V
2
11
/(f
SRC
/2)
62 KB / 2 KB
XX 59 KB / 4 KB
XY 53 KB / 8 KB
XZ 41 KB / 16 KB
XA 1.8 V
2
8
/(f
SRC
/2)
62 KB / 2 KB
XB 59 KB / 4 KB
XC 53 KB / 8 KB
XD 41 KB / 16 KB
* ROM name: XA/XB/XC/XD/XW/XX/XY/XZ indicates the product that ReRAM is blank.
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
Publication date: October 2014 2
PubNo. 21705-019E
1.2 Hardware Features
Features
In this document, the divided clock and the frequency of it are described as follows:
Divided clock:Clock name/n (n: division ratio)
Frequency: f
Clock name
•CPU Core
- AM13L core
- LOAD-STORE architecture (3- or 4-stage Pipeline)
• Machine Cycle and Operating Voltage
- High-Speed mode
100 ns / 10 MHz (Max) (V
DD30
: 1.8 V to 3.6 V)
1.0 s / 1 MHz (Max) (V
DD30
: 1.3 V to 3.6 V)
- Low-Speed Mode
25 s / 40 kHz (Max) (V
DD30
: 1.1 V to 3.6 V)
• Operating Mode
- NORMAL mode (High-Speed mode)
- SLOW mode (Low-Speed mode)
- HALT mode (High-Speed/Low-Speed mode)
- STOP mode
• Embedded Memory
- ROM (ReRAM): 64 KB (Programmable area and Data area vary depending on the ROM name.
For details, see Table:1.1.1.)
- RAM: 4 KB
• ReRAM Specification
- Program voltage (V
DD30
): 1.8 V to 3.6 V
- Program cycles: 1000 times (Program area), 100000 times (Data area)
- Data is rewritable in bytes without data erase.
• Clock Oscillator (4 circuits)
- External Low-Speed Oscillation (SOSCCLK): 32.768 kHz (crystal or ceramic)
- External High-Speed Oscillation (HOSCCLK): up to 10 MHz (crystal or ceramic)
- Internal Low-Speed Oscillation (SRCCLK): 40 kHz ± 20 % (V
DD30
: 1.1 V to 3.6 V)
- Internal High-Speed Oscillation (HRCCLK): 10/8 MHz ± 3 % (V
DD30
: 1.8 V to 3.6 V)
1 MHz ± 10 % (V
DD30
: 1.3 V to 3.6 V)
* MN101LR02D does not have external high-speed oscillation (HOSCCLK).
• Internal Operating Clock
- System Clock (SYSCLK): 10 MHz (Max)
SYSCLK is generated by dividing HCLK or SCLK, and the division ratio is 1, 2, 4, 8, 16 or 32.
HCLK: HOSCCLK or HRCCLK
SCLK: SOSCCLK or SRCCLK
* MN101LR02D cannot be selected HOSCCLK.
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
Publication date: October 2014 3
PubNo. 21705-019E
• Interrupt Circuit
MN101LR05D/04D/03D: 31 internal interrupts (except for NMI)
8 external interrupts (IRQ interrupt: 7, KEY interrupt: 1)
MN101LR02D: 29 internal interrupts (except for NMI)
3 external interrupts (IRQ interrupt: 2, KEY interrupt: 1)
• DMA (1 channel)
- Data transfer size: 8 bits/16 bits
- Maximum transfer counts: 1023
- Activation trigger: external interrupts / internal interrupts / software (setting the DMA start bit)
• Watchdog Timer (WDT)
- Function: 1st watchdog time-out generates NMI, and 2nd consecutive time-out generates a LSI reset.
- Clock Source: WDTCLK (SOSCCLK or SRCCLK)
• Timer Counter: 13 units
- General-purpose 8-bit timer (Timer 0/1/2/3/4/5): 6 units
- General-purpose 16-bit timer (Timer 7/8/9): 3 units
- 8-bit free-run (Timer 6) /Time-base timer: 1 unit each
- RTC time base timer (RTC-TBT): 1 unit
- Real Time Clock (RTC): 1 unit
<Timer 0>
- Function: Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM0IO input
<Timer 1 >
- Function: Square wave output, event count, 16-bit cascade connection (connected with Timer 0)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM1IO input
<Timer 2>
- Function: Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM2IO input
* MN101LR02D cannot be used simple pulse width measurement.
<Timer 3 >
- Function: Square wave output, event count, 16-bit cascade connection (connected with Timer 2)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM3IO input
<Timer 4>
- Function: Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM4IO input
<Timer 5 >
- Function: Square wave output, event count, 16-bit cascade connection (connected with Timer 4)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM5IO input
* MN101LR02D cannot be used square wave output, event count and TM5IO.
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MN101LR05DXW

Mfr. #:
Buy MN101LR05DXW
Manufacturer:
Panasonic
Description:
8-bit Microcontrollers - MCU ROM 64KB, RAM 4KB 80-TQFP ReRAM MCU
Lifecycle:
New from this manufacturer.
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