P89LPC932A1FDH,529 Datasheet P89LPC932A1FA,129, P89LPC932A1FDH,529, P89LPC932A1FHN,151 | P10-P12

Product data sheet Rev. 03 — 12 March 2007 10 of 64

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P2.7/ICA 28 24 I/O P2.7 — Port 2 bit 7.

I ICA — Input Capture A.

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type.

During reset Port 3 latches are conﬁgured in the input only mode with the

internal pull-up disabled. The operation of Port 3 pins as inputs and

outputs depends upon the port conﬁguration selected. Each port pin is

conﬁgured independently. Refer to

Section 7.13.1 “Port conﬁgurations”

and

Table 8 “Static characteristics” for details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

P3.0/XTAL2/

CLKOUT

9 5 I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator

option is selected via the ﬂash conﬁguration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -

TRIM.6). It can be used if the CPU clock is the internal RC oscillator,

watchdog oscillator or external clock input, except when XTAL1/XTAL2 are

used to generate clock source for the RTC/system timer.

P3.1/XTAL1 8 4 I/O P3.1 — Port 3 bit 1.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits

(when selected via the ﬂash conﬁguration). It can be a port pin if internal

RC oscillator or watchdog oscillator is used as the CPU clock source, and

if XTAL1/XTAL2 are not used to generate the clock for the RTC/system

timer.

73IGround: 0 V reference.

21 17 I Power supply: This is the power supply voltage for normal operation as

well as Idle and Power-down modes.

Table 2. Pin description

…continued

Symbol Pin Type Description

TSSOP28,

PLCC28,

DIP28

HVQFN28

Product data sheet Rev. 03 — 12 March 2007 11 of 64

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

7. Functional description

Remark: Please refer to the P89LPC932A1

User manual

for a more detailed functional

description.

7.1 Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with logic 0, but can return any

value when read (even if it was written with logic 0). It is a reserved bit and may be

used in future derivatives.

– Logic 0 must be written with logic 0, and will return a logic 0 when read.

– Logic 1 must be written with logic 1, and will return a logic 1 when read.

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Product data sheet Rev. 03 — 12 March 2007 12 of 64

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

Table 3. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

addr.

Bit functions and addresses Reset value

MSB LSB Hex Binary

Bit address E7 E6 E5 E4 E3 E2 E1 E0

ACC* Accumulator E0H 00 0000 0000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

B* B register F0H 00 0000 0000

BRGR0 Baud rate generator rate low BEH 00

[1]

0000 0000

BRGR1 Baud rate generator rate high BFH 00

[1]

0000 0000

BRGCON Baud rate generator control BDH ------SBRGS BRGEN 00

[1]

xxxx xx00

CCCRA Capture compare A control

EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1 OCMA0 00 0000 0000

CCCRB Capture compare B control

EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1 OCMB0 00 0000 0000

CCCRC Capture compare C control

ECH-----FCOC OCMC1 OCMC0 00 xxxx x000

CCCRD Capture compare D control

EDH-----FCOD OCMD1 OCMD0 00 xxxx x000

CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00

[2]

xx00 0000

CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00

[2]

xx00 0000

DEECON Data EEPROM control

F1H EEIF HVERR ECTL1 ECTL0 - - - EADR8 0E 0000 1110

DEEDAT Data EEPROM data register F2H 00 0000 0000

DEEADR Data EEPROM address

F3H 00 0000 0000

DIVM CPU clock divide-by-M

control

95H 00 0000 0000

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H 00 0000 0000

DPL Data pointer low 82H 00 0000 0000

I2ADR I

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

Bit address DF DE DD DC DB DA D9 D8

I2CON* I

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P64

P89LPC932A1FDH,529

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Manufacturer:

NXP Semiconductors

Description:

IC MCU 8BIT 8KB FLASH 28TSSOP

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P89LPC932A1FDH,529

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