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ICS650R-11I

P1-P3P4-P6
ICS650-11C
MDS 650-11C 1 Rev H 102709
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
Alcatel Clock Source
Description
The ICS650-11C is a low-cost, low-jitter,
high-performance clock synthesizer optimized for
Alcatel system requirements. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a parallel resonant 17.664 MHz crystal input to
produce up to five output clocks.
Features
• Packaged in 20-pin tiny SSOP (QSOP)
• Operating VDD of 3.3 V
• Inexpensive 17.664 MHz crystal or clock input
• Provides selectable 80 MHz or 78.9 MHz clock
• Provides selectable 59.23 MHz clock
• Provides selectable 25 MHz or 33 MHz clock
• Provides selectable 70.6 MHz or 50.78 MHz clock
• Provides fixed 17.664 MHz clock
• Duty cycle of 40/60
• Advanced, low-power CMOS process
• Industrial temperature range
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
Crystal
Oscillator
Clock
Synthesis
Circuitry
17.664 MHz
crystal
SEL-P
25 MHz or 33 MHz
80 MHz or 78.9 MHz
17.664 MHz
X1
X2
VDD GND
SB0:1
SC0:1
59.23 MHz
70.6 MHz or 50.78 MHz
Alcatel Clock Source
MDS 650-11C 2 Rev H 102709
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-11C
Pin Assignment
Processor Clock (MHz)
0 = connect directly to ground
1 = connect directly to VDD
SC Clock (MHz)
SB Clock (MHz)
Pin Descriptions
13
4
12
5
11
SB1
8
9
10
VDD
80M/78.9M
17.664M
SC1
DC 25/33M
17
16
70.6M/50.78M
3X1
VDD DC
18 DC
1SB0
X2 SEL-P
20 GND
19
14
2
7
GND
59.23M
SC0
GND
156
20-pin (150 mil) SSOP
SEL-P Pin 12
033.0
125.0
SC1 SC0 Pin 10
00 OFF
0 1 70.656
1 0 50.784
SB1 SB0 Pin 7 Pin 8
00 Low 80
1159.23 78.9
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 SB0 Input Input pin. See table above.
2 X2 XO Crystal connection. Connect to a parallel mode 17.664 MHz crystal. Leave
open for clock.
3 X1 XI Crystal connection. Connect to a parallel mode 17.664 MHz crystal or clock.
4, 16 VDD Power Connect to VDD. Must be same value as other VDD’s. Decouple with pin 6.
5 SB1 Input Select pin. See table above.
6, 14, 20 GND Power Connect to ground.
7 59.32M Output B1 clock. See table above.
8 80M/78.9M Output B2 clock. See table above.
9, 17, 18 DC — Don’t connect. Do not connect this pin to anything.
10 70.6M/50.78M Output SC clock. See table above.
11 SC1 Input Select pin. See table above.
12 25/33M Output 25 MHz or 33 MHz clock output. Determined by SEL-P per table above.
13 17.664M Output 17.664 MHz buffered reference clock output.
15 SC0 Input Select pin. See table above.
19 SEL-P Input Select pin. Determines frequency of pin 12 per table above.
Alcatel Clock Source
MDS 650-11C 3 Rev H 102709
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-11C
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS650-11C must be isolated from system power
supply noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS650-11C. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
P1-P3P4-P6

ICS650R-11I

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IC NETWORKING CLK SOURCE 20-SSOP
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