11
3672A–CNFG–1/08
AT18F010/002/040/080 [Preliminary]
12. AC Characteristics
Figure 12-1. AT18Fxx as Configuration Slave with CLK Input Pin as Clock Source
Table 12-1. AC Characteristics over Operating Conditions
Symbol Description Min Max
Units
T
CF
CF to Data Delay 20 50 µs
T
OE
RESET/OE to Data Delay 10 ns
T
CE
CE to Data Delay 20 µs
T
CAC
CLK to Data Delay 15 ns
T
OH
Data Hold from CE, RESET/OE, CLK, or CF 15 ns
T
DF
CE or RESET/OE to Data Float Delay 25 ns
T
CYC
Clock Period 30 ns
T
LC
CLK Low Time 15 ns
T
HC
CLK High Time 15 ns
T
SCE
CE Setup Time to CLK 20 µs
T
HCE
CE Hold Time 250 ns
T
HOE
RESET/OE Hold Time 250 ns
T
BLKE
Block Erase Time 0.7 1 s
T
ERASE
Bulk Erase Time – 1M 3s
Bulk Erase Time – 2M 5s
Bulk Erase Time – 4M 9s
Bulk Erase Time – 8M 15 s
T
CK_J
TAP Clock Minimum Period 100 ns
CE
RESET/OE
CLK
DATA
T
SCE
T
LC
T
HC
T
CYC
T
CAC
T
OE
T
CE
T
OH
T
HOE
T
CF
T
HCE
T
DF
T
OH
CF
