74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 14 May 2013 9 of 18
NXP Semiconductors
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
t
h
hold time nDn to nLE; see Figure 9
V
CC
= 1.65 V to 1.95 V 2.5 - - 2.5 - ns
V
CC
= 2.3 V to 2.7 V 2.0 - - 2.0 - ns
V
CC
= 2.7 V 0.9 - - 0.9 - ns
V
CC
= 3.0 V to 3.6 V +0.9 1.0 - +0.9 - ns
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per input; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 10.8 - - - pF
V
CC
= 2.3 V to 2.7 V - 13.0 - - - pF
V
CC
= 3.0 V to 3.6 V - 15.0 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions T
amb
= 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 14 May 2013 10 of 18
NXP Semiconductors
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
11. AC waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Input (nDn) to output (nQn) propagation delays
mna429
nDn input
nQn output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7. Latch enable (nLE) pulse width, and the latch enable input to output (nQn) propagation delays
mna430
nLE input
nQn output
t
PHL
t
W
GND
V
I
V
M
V
M
V
OH
V
OL
t
PLH
74LVC_LVCH162373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 14 May 2013 11 of 18
NXP Semiconductors
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. 3-state enable and disable times
mna432
t
PZL
t
PZH
t
PHZ
t
PLZ
GND
GND
V
I
V
CC
V
OL
V
OH
V
M
V
M
V
M
V
X
V
Y
outputs
disabled
outputs
enabled
outputs
enabled
nQn
output
LOW-to-OFF
OFF-to-LOW
nQn
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable
output performance.
Fig 9. Data set-up and hold times for the nDn input to the nLE input
mna431
t
h
t
su
nDn input
GND
V
I
V
M
t
h
t
su
nLE input
GND
V
I
V
M
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
V
X
V
Y
1.2 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
1.65 V to 1.95 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.3 V to 2.7 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.7 V 2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V

74LVC162373ADL,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Latches 3.3V 16 D-TP TRNSP
Lifecycle:
New from this manufacturer.
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