PLR233 Datasheet PLR233 | P7-P8

LifecyclePhase:

Revision : 2

Expired Period: Forever

Release Date:2013-05-30 14:26:12.0

DATASHEET

Photolink- Fiber Optic Receiver

PLR233 Series

www.everlight.com

RoHS

CPN :

P N :

PLR233

QTY :

LOT NO :

Reference :

CAT :

HUE :

REF :

EVERLIGHT

Label Explanation

CPN: Customer’s Product Number‧

P/N: Product Number‧

QTY: Packing Quantity‧

CAT: Luminous Intensity Rank‧

HUE: Dom. Wavelength Rank‧

REF: Forward Voltage Rank‧

LOT No: Lot Number‧

‧

X: Month

Reference: Identify Label Number

‧

Packing Quantity Specification

1. 250 pcs/bag

2. 4 bag/box

Notes

1. Above specification may be changed without notice. EVERLIGHT will reserve authority on material change for above

specification.

2. When using this product, please observe the absolute maximum ratings and the instructions for using outlined in these

specification sheets. EVERLIGHT assumes no responsibility for any damage resulting from use of the product which

does not comply with the absolute maximum ratings and the instructions included in these specification sheets.

3. These specification sheets include materials protected under copyright of EVERLIGHT corporation. Please don’t

reproduce or cause anyone to reproduce them without EVERLIGHT’s consent.

EVERLIGHT ELECTRONICS CO., LTD. Tel: 886-2-2685-6688

Office: No 6-8,Zhonghua Rd., Shulin Dist., Fax: 886-2-2685-6897

New Taipei City 23860, Taiwan, R.O.C http://www.everlight.com

LifecyclePhase:

Revision : 2

Expired Period: Forever

Release Date:2013-05-30 14:26:12.0

DATASHEET

Photolink- Fiber Optic Receiver

PLR233 Series

www.everlight.com

Application Notes: PLR233 Series PCB layout for motherboard integration

To achieve better jitter and low input optical power performances, several PCB layout guidelines must be followed.

These guidelines ensure the most reliable PLR233 SERIESPOF performance for the motherboard integration. Failed to

implement these PCB guidelines may affect the PLR231 jitter and low input power performances.

1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size 805 or smaller) capacitor

as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf act as a low impedance path to ground for any

stray high frequency transient noises.

2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance formed by an isolated Vcc

and Gnd planes is critical. The POF device must be mounted directly on these two planes to reduce the lead parasitic

inductance.

3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at a single point using

ferrite beads. The beads are used to block the high frequency noises from the digital planes while still allowing the DC

connections between the planes

P1-P3 P4-P6 P7-P8

PLR233

Mfr. #:

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Description:

Fiber Optic Transmitters, Receivers, Transceivers Photo Link

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