MAX1512
To avoid unintentional VCOM adjustment, the MAX1512
is guaranteed to reject CTL pulses shorter than 20µs. In
addition, to avoid the possibility of a single false pulse
caused by power-up sequencing between V
DD
and
CTL, the very first pulse is ignored.
EEPROM Programming (CTL)
To program the EEPROM, apply the EEPROM program-
ming waveform through the CTL interface (Figure 7).
The control interface delivers programming power and
DAC adjustment commands on the same wire. This
single-wire approach minimizes the number of connec-
tions from the programming circuit to the LCD panel.
To apply the EEPROM programming waveform, carefully
ramp CTL from midscale (V
DD
/ 2) to the programming
voltage, V
PP
, in 7.5ms as shown in Figure 7. If the ramp
is generated digitally, use at least 45 steps to achieve
the required 320mV ramp resolution. During the ramp
time, VCOM adjustment is disabled and the EEPROM
cells are biased in preparation for programming. After
reaching V
PP
, hold CTL at V
PP
for 1ms. During the
EFPROM program time, the EEPROM stores the DAC
setting. Next, drive CTL to ground in less than 1ms and
hold for at least 200µs. Finally, drive CTL to V
DD
/ 2 to
complete the write cycle. The EEPROM is factory set to
half scale. Follow the EEPROM Programming Spec-
ifications in Table 1 to guarantee reliable EEPROM pro-
gramming. Violating the specifications can damage the
EEPROM or affect data retention.
A complete evaluation kit is available to simplify evalua-
tion and production development.
EEPROM-Programmable TFT VCOM Calibrator
10 ______________________________________________________________________________________
Table 1. EEPROM Programming Specifications
PARAMETER SYMBOL MIN TYP MAX UNITS
CTL Programming Voltage V
PP
15.25 15.5 15.75 V
CTL Programming Ramp T1 7.0 7.5 8.0 ms
EEPROM Program Time T2 0.9 1.0 1.1 ms
V
PP
Fall Time T3 10 1000 µs
Done Hold Time T4 200 µs
0
V
PP
CTL VOLTAGE
TIME
V
DD
/ 2
T1
T2 T4T3
Figure 7. EEPROM Programming
Applications Information
The VCOM adjustment and the EEPROM programming
must be performed with an external programming cir-
cuit. Refer to the MAX1512 evaluation kit for a complete
programming circuit solution.
Use a circuit similar to the conceptual diagram shown in
Figure 8 to drive CTL. The accuracy of the programming
voltage (V
PP
) is critical for proper MAX1512 data reten-
tion. The use of a comparator is recommended to verify
the correct programming voltage has been reached. A
complete design example of a CTL programming circuit
is presented in the MAX1512 evaluation kit data sheet.
Electrostatic Discharge (CTL, CE)
Often, CTL and CE are exposed at the panel connector
and are therefore subject to electrostatic discharge
(ESD). Resistor-capacitor (RC) filters can be employed
at these inputs to improve their ESD performance
(Figure 9).
If the CE panel connector is to be left floating after pro-
gramming, be sure to include a resistor to ground (R
CE
)
to ensure a valid logic-low on CE. The time constant for
a CE filter is not critical but the driving resistor must
have a much lower resistance than RCE to properly
drive CE.
If a filter is used at the CTL panel connector, its RC time-
constant should be short enough to avoid interfering with
CTL pulses or EEPROM programming timing. A time
constant less than 200µs does not interfere with EEP-
ROM programming. To avoid interfering with CTL puls-
es, make the time constant small compared to the CTL
pulsewidth used.
Leakage Current (CTL)
The CTL pin is internally biased to V
DD
/ 2, but it is sen-
sitive to leakage currents above 0.1µA. When CTL is
not driven, avoid leakage currents around the CTL pin.
Otherwise, reinforce the V
DD
/ 2 set point with an exter-
nal resistive voltage-divider.
Layout Information
Use the following guidelines for good layout:
Place the VCOM buffer and the R1/R2 voltage-
divider close to the OUT pin (Figure 1). Keep the
VCOM buffer and the R1/R2 voltage-divider close
to each other.
Place R
SET
close to SET.
In noisy environments, bypass capacitors may be
desired on V
DD
and/or V
AVDD
. Keep any bypass
capacitors close to the IC with short connections to
the pins.
Refer to the MAX1512 evaluation kit for an example of
proper board layout.
MAX1512
EEPROM-Programmable TFT VCOM Calibrator
______________________________________________________________________________________ 11
DAC
0 TO 2.5V
µC
USER
INTERFACE
CTL
MAX1512
REF
0 TO 15.5V
V
PP
VERIFY
Figure 8. Conceptual Programming Circuit
V
DD
GND
CTL
CE
1k
R
CE
100k
0.1µF
0.1µF
V
DD
DURING
PROGRAMMING,
FLOATING AFTER
PROGRAMING
FLOATING AFTER
PROGRAMMING
10k
MAX1512
Figure 9. Improved EOS/Surge Performance
MAX1512
EEPROM-Programmable TFT VCOM Calibrator
12 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
6, 8, &10L, DFN THIN.EPS
H
1
2
21-0137
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm

MAX1512ETA+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
LCD Gamma Buffers EEPROM-Prog TFT VCOM Calibrator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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