ADA4320-1
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Table 4.
Parameter Rating
Supply Voltage 5.5 V
Maximum Power Dissipation 1.65 W
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
The maximum safe power dissipation in the ADA4320-1 package
is limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the ADA4320-1. Exceeding a junction temperature
of 150°C for an extended time can result in changes in the silicon
devices, potentially causing failure.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes,
reduces the θ
JA
. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θ
JA
.
THERMAL RESISTANCE
θ
JA
is specified for the device soldered to a high thermal
conductivity 4-layer (2s2p) circuit board, as described in
EIA/JESD 51-7.
ESD CAUTION
Table 5. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
24-lead LFCSP 31.2 5.7 °C/W
ADA4320-1
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
82
92
10 22
11 21
12
GND
GND
VIN–
VIN+
GND 20
COMP
VOUT
4
3
+
VOUT
VOUT
+
VOUT
19
18
17
16
15
14
1
2
3
4
5
6
7
GND
GND
VCC
VCC
VCC
RAMP
TXEN 13
GND
GND
GND
SLEEP
CLK
SDATA
DATEN
ADA4320-1
TOP VIEW
(Not to Scale
NOTES
1. EXPOSED THERMAL PAD MUST BE ELECTRICALLY AND
THERMALLY CONNECTED TO PCB GROUND (GND) PLANE.
08707-005
Figure 4. Pin Configuration, Top View
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 8, 9, 12,
17, 18, 19,
EPAD
GND Common External Ground Reference.
3, 4, 5 VCC Common Positive External Supply Voltage.
6 RAMP External RAMP Capacitor (Optional).
7 TXEN Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission.
10 VIN− Inverting Input. DC-biased to approximately V
CC
/2. This pin should be ac-coupled with a 0.1 µF capacitor.
11 VIN+ Noninverting Input. DC-biased to approximately V
CC
/2. This pin should be ac-coupled with a 0.1 µF capacitor.
13
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition
transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer
into the register. A 1-to-0 transition inhibits the data latch (holds the previous, and simultaneously enables the
register for serial data load).
14 SDATA
Serial Data Input. This digital input allows an 8-bit serial control word to be loaded into the internal register with the
most significant bit (MSB) first to adjust both the gain and current levels.
15 CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. A
Logic 0-to-1 transition latches the data bit, and a Logic 1-to-0 transition transfers the data bit to the slave. This
requires the input serial data-word to be valid at or before this clock transition.
16
SLEEP
Low Power Sleep Mode. In sleep mode, the supply current is reduced to 12 µA typical. Logic 0 powers down
the device, and Logic 1 powers up the device.
20, 22 VOUT− Negative Output Signal. This pin must be biased to V
CC
.
21, 23 VOUT+ Positive Output Signal. This pin must be biased to V
CC
.
24 COMP Internal Compensation. This pin must be externally decoupled (0.1 F capacitor).
ADA4320-1
Rev. A | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, V
S
= 5 V, R
L
= 75 Ω, V
IN
(differential) = 29 dBmV sinusoidal, f = 5 MHz to 85 MHz, Gain Code 60 (maximum), Current Level 3
(maximum), V
OUT
(single-ended) measured at output of Coilcraft PWB-4-BL transformer, unless otherwise noted.
300
50
100
150
200
250
0 6 12 18 24 30 36 42 48 54 60
SUPPLY CURRENT (mA)
GAIN CODE
CURRENT LEVEL 3
CURRENT LEVEL 2
CURRENT LEVEL 1
CURRENT LEVEL 0
V
IN
= 29dBmV
08707-006
Figure 5. Supply Current vs. Gain Code
275
270
265
260
255
250
245
240
235
–60 –40 –20 0 20 40 60 80 100
SUPPLY CURRENT (mA)
AMBIENT TEMPERATURE (°C)
GAIN CODE 60
CURRENT LEVEL 3
5.25V
5.00V
4.75V
08707-007
Figure 6. Supply Current vs. Ambient Temperature at Maximum Gain
75
70
65
60
55
50
–60 –40 –20 0 20 40 60 80 100
SUPPLY CURRENT (mA)
AMBIENT TEMPERATURE (°C)
GAIN CODE 01
CURRENT LEVEL 0
5.25V
5.00V
4.75V
08707-008
Figure 7. Supply Current vs. Ambient Temperature at Minimum Gain
60
–60
–45
–30
–15
0
15
30
45
1M 1G100M10M
GAIN (dB)
FREQUENCY (Hz)
CURRENT LEVEL 3
V
IN
= 29dBmV
GAIN CODE 60
GAIN CODE 40
GAIN CODE 20
GAIN CODE 01
08707-009
Figure 8. Gain vs. Frequency
1.0
–2.0
–1.5
–1.0
–0.5
0
0.5
58807570656055504540353025201510
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
5
CURRENT LEVEL 3
CURRENT LEVEL 2
CURRENT LEVEL 1
CURRENT LEVEL 0
GAIN CODE 60 (MAXIMUM)
V
IN
= 29dBmV
08707-010
Figure 9. Normalized Frequency Response at Maximum Gain
1.0
–3.0
–2.0
–2.5
–1.5
–1.0
–0.5
0
0.5
58807570656055504540353025201510
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
5
+25°C
–40°C
+85°C
GAIN CODE 60 (MAXIMUM)
V
IN
= 29dBmV
08707-011
Figure 10. Normalized Frequency Response over Temperature

ADA4320-1ACPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video Amplifiers 5V DOCSIS 3.0 Low Distort Line Dvr
Lifecycle:
New from this manufacturer.
Delivery:
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