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TS110-7A1-AP

P1-P3P4-P6P7-P9P10-P10
Characteristics TS110-7
4/10 DocID022271 Rev 4
Figure 5. Relative variation of thermal
impedance junction to ambient versus pulse
duration
Figure 6. Relative variation of gate triggering
current and voltage, holding and latching
current versus T
j
K=[Z /R ]
th(j-a) th(j-a)
0.01
0.10
1.00
1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
TO-92
SMBflat-3L
Copper surface
area = 5cm²
t (s)
p
I,I,I [T] /
GT H L j
, V I , I , I , V [T =25°C]
GT GT H L GT j
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
-40 -20 0 20 40 60 80 100 120
V
GT
I
GT
I
H
& I
L
T (°C)
j
Figure 7. Relative variation of holding current
versus gate-cathode resistance (typical values)
Figure 8. Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
I [R ] / I [ = 220 ]
HGK H
ΩR
GK
0.0
0.5
1.0
1.5
0.1 1.0 10.0
R(k)
GK
Ω
dV/dt[R ] / dV/dt[R = 220 ]
GK GK
W
0.01
0.10
1.00
10.00
0 200 400 600 800
R()
GK
W
T = 125°C
j
V = 0.67 x V
D DRM
Figure 9. Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical
values)
Figure 10. Relative variation of dV/dt immunity
versus junction temperature with R
GK
= 220 Ω
(typical values)
dV/dt[C ] / dV/dt[C = 100 nF]
GK GK
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 20 40 60 80 100 120 140 160 180 200 220
C (nF)
GK
T
j
= 125°C
V = 0.67 x V
D DRM
Typical value of dV/dt = 25 V/µs[C
GK
=
100 nF]
dV/dt[ ] / dV/dt[ = ]T
j
T
j
125 °C
0
1
2
3
4
5
6
7
8
9
10
20 40 60 80 100 120
T (°C)
j
R
GK
= 220
V = 0.67 x V
Ω
D DRM
DocID022271 Rev 4 5/10
TS110-7 Characteristics
10
Figure 11. Surge peak on-state current versus
number of cycles
Figure 12. Non-repetitive surge peak on-state
current, and corresponding values of I
2
t
I(A)
TSM
0
2
4
6
8
10
12
14
16
18
20
22
24
26
1 10 100 1000
Non repetitive
T
j
initial=25 °C
SMBF-3L
Repetitive
T
A
=25 °C
TO-92
Repetitive
T
A
=25 °C
Number of cycles
t =10ms
p
One cycle
I (A), I t (A s)
TSM
22
1
10
100
1000
0.01 0.10 1.00 10.00
I
TSM
I²t
T
j
initial=25 °C
t (ms)
p
Sinusoidal pulse with
width tp < 10 ms
Figure 13. On-state characteristics (maximum
values)
Figure 14. Thermal resistance junction to
ambient versus copper surface under anode
(SMBflat-3L)
I (A)
TM
0.1
1.0
10.0
100.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
T
j
max :
V
to
=0.9 V
R
d
=200 mΩ
T
J
=125°C
T
J
=25°C
V (V)
TM
R (°C/W)
th(j-a)
50
60
70
80
90
100
110
120
130
140
150
160
170
012345
S(cm²)
Epoxy printed circuit board FR4
copper thickness = 35 µm
AC line transient voltage ruggedness TS110-7
6/10 DocID022271 Rev 4
2 AC line transient voltage ruggedness
In comparison with standard SCRs, the TS110-7 is self-protected against over-voltage. The
TS110-7 switch can safely withstand AC line surge voltages by switching to the on state (for
less than 10 ms on 50 Hz mains) to dissipate energy shocks through the load. The load
limits the current through the TS110-7. The self-protection against over-voltage is based on
an overvoltage crowbar technology. This safety feature works even with high turn-on current
ramp up.
Figure 15 represents the TS110-7 in a test environment. It is used to stress the TS110-7
switch according to the IEC 61000-4-5 standard conditions. The TS110-7 folds back safely
to the on state as shown in Figure 16.
The TS110-7 recovers its blocking voltage capability after the surge and the next zero
current crossing. Such a non repetitive test can be done at least 10 times.
Figure 15. Overvoltage ruggedness test circuit for IEC 61000-4-5 standards
Figure 16. Typical current and voltage waveforms across the TS110-7 during
IEC 61000-4-5 standard test
AC Mains
R
1
R
2
Filtering unit
Model of the load
Surge generator
60 Ω 60 Ω
12 Ω
C
IN
150 nF
47 nF
TS110
I
T
V
T
I
V
0
0
V
peak
=V
BO
1.2/50 µs voltage surge
I
peak
= 25 A
dI/dt = 100 A/µs
P1-P3P4-P6P7-P9P10-P10

TS110-7A1-AP

Mfr. #:
Buy TS110-7A1-AP
Manufacturer:
STMicroelectronics
Description:
SCRs High surge voltage 1.25 A SCR for circuit breaker
Lifecycle:
New from this manufacturer.
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