AD8009ARZ Datasheet AD8009JRTZ-REEL7, AD8009ARZ, AD8009ARZ-REEL7 | P13-P15

AD8009

–12–

REV. F

10F

0.1F

AD8009

75

301

10F0.1F

–5V

AD8009

75

301

AD8009

75

301

75 COAX

PRIMARY MONITOR

ADDITIONAL MONITOR

75 COAX

75

RED

GREEN

BLUE

RED

GREEN

BLUE

OUT

ADV7160/

ADV7162

Figure 4. Driving an Additional High Resolution Monitor Using Three AD8009s

RGB Monitor Driver

High resolution computer monitors require very high full power

bandwidth signals to maximize their display resolution. The

RGB signals that drive these monitors are generally provided by

a current-out RAMDAC that can directly drive a 75 Ω doubly

terminated line.

There are times when the same output wants to be delivered to

additional monitors. The termination provided internally by

each monitor prohibits the ability to simply connect a second

monitor in parallel with the first. Additional buffering must be

provided.

Figure 4 shows a connection diagram for two high resolution

monitors being driven by an ADV7160 or ADV7162, a 220 MHz

(Megapixel per second) triple RAMDAC. This pixel rate

requires a driver whose full power bandwidth is at least half the

pixel rate or 110 MHz. This is to provide good resolution for a

worst-case signal that swings between zero scale and full scale

on adjacent pixels.

The primary monitor is connected in the conventional fashion

with a 75 Ω termination to ground at each end of the 75 Ω

cable. Sometimes this configuration is called “doubly termi-

nated” and is used when the driver is a high output impedance

current source.

For the additional monitor, each of the RGB signals close to the

RAMDAC output is applied to a high input impedance, noninvert-

ing input of an AD8009 that is configured for a gain of +2. The

outputs each drive a series 75 Ω resistor, cable, and termination

resistor in the monitor that divides the output signal by two, thus

providing an overall unity gain. This scheme is referred to as

“back termination” and is used when the driver is a low output

impedance voltage source. Back termination requires that the

voltage of the signal be double the value that the monitor sees.

Double termination requires that the output current be double the

value that flows in the monitor termination.

–13–

REV. F

AD8009

Driving a Capacitive Load

A capacitive load, like that presented by some A/D converters,

can sometimes be a challenge for an op amp to drive depending

on the architecture of the op amp. Most of the problem is caused

by the pole created by the output impedance of the op amp and

the capacitor that is driven. This creates extra phase shift that

can eventually cause the op amp to become unstable.

One way to prevent instability and improve settling time when

driving a capacitor is to insert a resistor in series between the

op amp output and the capacitor. The feedback resistor is still

connected directly to the output of the op amp, while the series

resistor provides some isolation of the capacitive load from the

op amp output.

10F

0.1F0.001F

10F

0.1F

0.001F

AD8009

49.9

+5V

–5V

50pF

STEP

G = +2: R

= 301 = R

G = +10: R

= 200, R

= 22.1

Figure 5. Capacitive Load Drive Circuit

Figure 5 shows such a circuit with an AD8009 driving a 50 pF

load. With R

= 0, the AD8009 circuit will be unstable. For a

gain of +2 and +10, it was found experimentally that setting R

to 42.2 Ω will minimize the 0.1% settling time with a 2 V step at

the output. The 0.1% settling time was measured to be 40 ns with

this circuit.

For smaller capacitive loads, a smaller R

will yield optimal

settling time, while a larger R

will be required for larger capacitive

loads. Of course, a larger capacitance will always require more

time for settling to a given accuracy than a smaller one, and this

will be lengthened by the increase in R

required. At best, a

given RC combination will require about seven time constants

by itself to settle to 0.1%, so a limit will be reached where too

large a capacitance cannot be driven by a given op amp and still

meet the system’s required settling time specification.

AD8009

–14–

REV. F

OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

(R-8)

Dimensions shown in millimeters and (inches)

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

 45

8

0

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

5-Lead Small Outline Transistor Package [SOT-23]

(RT-5)

Dimensions shown in millimeters

PIN 1

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

1 3

4 5

0.22

0.08

10

5

0

0.50

0.30

0.15 MAX

SEATING

PLANE

1.45 MAX

1.30

1.15

0.90

2.90 BSC

0.60

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-178AA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD8009ARZ

Mfr. #:

Buy AD8009ARZ

Manufacturer:

Analog Devices Inc.

Description:

High Speed Operational Amplifiers 1GHz 5,500 V/uS Low Distortion

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AD8009ARZ

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