MAX3873AETP+

MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
4 _______________________________________________________________________________________
Figure 1. Definition of Input Voltage Swing
Figure 2. Definition of Clock-to-Q Delay
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
(b) DC-COUPLED SINGLE-ENDED CML INPUT
25mV
25mV
800mV
800mV
V
CC
+ 0.4V
V
CC
V
CC
- 0.4V
V
CC
V
CC
- 0.4V
V
CC
- 0.8V
SCLKO+
SDO
t
CLK
t
CLK-Q
Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time
INPUT DATA
FREQUENCY ACQUISITION TIME
LOL OUTPUT
LOL ASSERT TIME
Figure 3. Definition of Phase Acquisition Time
SERIAL DATA
1200 BITS OF 1–0 PATTERN
<2μs
FASTRACK
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, C
F
= 0.022µF, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, 2.488Gbps, T
A
= +25°C, unless otherwise
noted.) (Note 4)
Note 1: At T
A
= -40°C, DC characteristics are guaranteed by design and characterization.
Note 2: CML outputs open.
Note 3: R
L
= 50Ω to V
CC
.
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the falling edge of SCLKO+. See Figure 2.
Note 6: Measured with 2
23
- 1 PRBS.
Note 7: Jitter BW = 12kHz to 20MHz.
Note 8: RATESET = low.
Note 9: RATESET = high.
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
_______________________________________________________________________________________ 5
RECOVERED CLOCK AND DATA
(2.488Gbps, 2
23
- 1 PATTERN,
V
IN
= 50mV
P-P
)
MAX3873A toc01
125mV/div
100ps/div
RECOVERED CLOCK AND DATA
(2.67Gbps, 2
23
- 1 PATTERN,
V
IN
= 50mV
P-P
)
MAX3873A toc02
125mV/div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)
MAX3873A toc03
10ps/div
2
23
- 1 PATTERN
RMS = 2.0ps
RMS
100
10
1
0.1
10 100 1000 10,000
JITTER TOLERANCE
(2.488Gbps, 2
23
- 1 PATTERN,
V
IN
= 50mV
P-P
)
MAX3873A toc04
JITTER FREQUENCY (kHz)
INPUT JITTER (UIp-p)
BELLCORE
MASK
WITH 0.2UI OF PWD
WITH 0.4UI OF
DETERMINISTIC
JITTER
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
0.5
-3.0
JITTER TRANSFER
-1.5
MAX3873A toc05
FREQUENCY (Hz)
TRANSFER (dB)
-1.0
-0.5
0
10
3
10
5
10
6
10
4
10
7
-2.0
-2.5
BELLCORE
MASK
0
60
40
20
80
100
120
140
160
180
200
-50 0-25 25 50 75 100
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO DISABLED)
MAX3873A toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MED OUTPUT SWING
MAX OUTPUT SWING
MIN OUTPUT SWING
0
60
40
20
80
100
120
140
160
180
200
-50 0-25 25 50 75 100
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO ENABLED)
MAX3873A toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MED OUTPUT SWING
MAX OUTPUT SWING
MIN OUTPUT SWING
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
2.0
2.3
2.2
2.1
2.4
2.5
2.6
2.7
2.8
2.9
3.0
-50 0 50 100
PULLIN RANGE (RATESET = 0)
MAX3873A toc08
AMBIENT TEMPERATURE (°C)
FREQUENCY (GHz)
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
BIT-ERROR RATIO
vs. INPUT AMPLITUDE
MAX3873A toc09
INPUT VOLTAGE (mVp-p)
BIT ERROR RATIO
012345
10
-8
10
-9
10
-10
0
0.3
0.2
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.05 0.10 0.15 0.20
JITTER TOLERANCE vs. INPUT
DETERMINISTIC JITTER
MAX3873A toc10
DETERMINISTIC JITTER (UI
P-P
)
SINUSOIDAL JITTER TOLERANCE (UI
P-P
)
f
JITTER
= 1MHz
f
JITTER
= 10MHz
PRBS = 2
23
- 1
0
0.2
0.1
0.4
0.3
0.6
0.5
0.7
0.9
0.8
1.0
-40 -20 -10-30 0 10203040
JITTER TOLERANCE vs. PULSE-WIDTH
DISTORTION
MAX3873A toc11
INPUT PULSE-WIDTH DISTORTION (%)
SINUSOIDAL JITTER TOLERANCE (UI
P-P
)
PRBS = 2
23
- 1
f
JITTER
= 1MHz
f
JITTER
= 10MHz
INPUT DATA FILTERED BY
1870MHz 4TH-ORDER
BESSEL FILTER
PIN NAME FUNCTION
1 RATESET Input Rate Select. Connect to TTL low for 2.488Gbps data and to TTL high for 2.67Gbps data.
2, 5, 6 V
CC
3.3V Supply Voltage
3 SDI+ Positive Serial Data Input
4 SDI- Negative Serial Data Input
7 FASTRACK
PLL Fast Track Control, TTL Input. When FASTRACK is TTL high, the PLL is switched to a fast-
track mode for fast phase acquisition. When FASTRACK is TTL low, the PLL operates normally.
8 VCC_VCO 3.3V VCO Supply Voltage
9 MODE
Output Amplitude Mode Select. MODE = open sets the CML output amplitude to high; MODE =
high sets the output amplitude to medium; MODE = low sets the output amplitude to low.
Pin Description

MAX3873AETP+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Clock Generators & Support Products 2.5/2.7Gbps Clk-Reco & Data-Retiming IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet