LT3434
21
3434fb
APPLICATIO S I FOR ATIO
WUUU
Example: with V
IN
= 40V, V
OUT
= 5V and I
OUT
= 2A:
Pee
SW
=
( )()()
+
()
()
()( )
015 2 5
40
77 9 1 2 2 40 200
2
.
–/
33
008 062 07
5240
40
003
2
()
+=
=
()
()
=
...
/
.P
P
BOOST
Q
==
()
+
()
=40 0 0026 5 0 001 0 109...
Total power dissipation is:
P
TOT
= 0.7 + 0.03 + 0.109 = 0.84
Thermal resistance for the LT3434 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
J
= T
A
+ Q
JA
(P
TOT
)
With the FE16 package (Q
JA
= 45°C/W) at an ambient
temperature of 70°C:
T
J
= 70 + 45(0.84) = 108°C
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT3434
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation the actual maximum V
IN
achievable in a
particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switch-
ing loss is also proportional to the square of input voltage.
For example, while the combination of V
IN
= 40V, V
OUT
=
5V at 2A and f
OSC
= 200kHz may be easily achievable,
simultaneously raising V
IN
to 60V and f
OSC
to 700kHz is
not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the result-
ing increase in internal dissipation is of insufficient time
duration to raise die temperature significantly.
A second consideration is controllability. A potential limi-
tation occurs with a high step-down ratio of V
IN
to V
OUT
,
as this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
t
ON(MIN)
= V
OUT
+ V
F
/V
IN
(f
OSC
)
where:
V
IN
= input voltage
V
OUT
= output voltage
V
F
= Schottky diode forward drop
f
OSC
= switching frequency
A potential controllability problem arises if the LT3434 is
called upon to produce an on time shorter than its typical
value of 250ns. Feedback loop action will lower then
reduce the V
C
control voltage to the point where some sort
of cycle-skipping or Burst Mode behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V
IN
, high I
OUT
and high f
OSC
may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
IN
, low V
OUT
and high f
OSC
can result in an unacceptably short
minimum switch on time. Cycle skipping and/or Burst
Mode behavior will result although correct output volt-
age is usually maintained.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
