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844251BGI-14LF

P1-P3P4-P6P7-P9P10-P12P13-P14
ICS844251BGI-14 REVISION A June 6, 2016 7 ©2016 Integrated Device Technology, Inc.
ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Application Information
Crystal Input Interface
The ICS844251I-14 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
1 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 1. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100
. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm
C1
0.1uF
3.3V
3.3V
Crystal Input Interface
XTA L_ I N
XTA L_ OU T
Crystal Input Interface
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
ICS844251BGI-14 REVISION A June 6, 2016 8 ©2016 Integrated Device Technology, Inc.
ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS844251I-14 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
DD
and V
DDA
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 3 illustrates
this for a generic V
DD
pin and also shows that V
DDA
requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V
DDA
pin.
Figure 3. Power Supply Filtering
2.5V LVDS Driver Termination
Figure 4 shows a typical termination for LVDS driver in characteristic
impedance of 100 differential (50 single) transmission line
environment. For buffer with multiple LVDS driver, it is recommended
to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
V
DD
V
DDA
2.5V
10
Ω
10µF.01µF
.01µF
2.5V
LVDS Driver
R1
100
Ω
–
+
2.5V
50Ω
50Ω
100Ω Differential Transmission Line
ICS844251BGI-14 REVISION A June 6, 2016 9 ©2016 Integrated Device Technology, Inc.
ICS844251I-14 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Schematic Example
Figure 5 shows an example of ICS844251I-14 application schematic.
In this example, the device is operated at V
DD
= 2.5V. The decoupling
capacitor should be located as close as possible to the power pin.
The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF
and C2 = 27pF are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. For the LVDS output drivers, place a
100 resistor as close to the receiver as possible.
Figure 5. ICS844251I-14 Schematic Example
C2
27pF
RD1
Not Install
U1
1
2
3
4
8
7
6
5
VDDA
GND
XTAL_OUT
XTAL_IN
VDD
Q
nQ
FREQ_SEL
R4
50
C3
0.1u
Zo = 50 Ohm
To Logic
Input
pins
FREQ_SEL
VDDA
C7
0.1uF
C1
27pF
RU1
1K
Set Logic
Input to
'0'
VDD
Alternate
LVDS
Termination
R3
50
VDD
Zo = 50 Ohm
Zo = 50 Ohm
VDD
+
-
Set Logic
Input to
'1'
VDD
+
-
Q
Zo = 50 Ohm
nQ
C4
10u
C5
0.01u
Logic Input Pin Examples
X1
25 MHz
nQ
RD2
1K
RU2
Not Install
To Logic
Input
pins
R1
10
Q
R2
100
P1-P3P4-P6P7-P9P10-P12P13-P14

844251BGI-14LF

Mfr. #:
Buy 844251BGI-14LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVDS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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