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74AUP2G241GS,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
74AUP2G241 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 11 February 2013 12 of 26
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
C
L
= 30 pF
t
pd
propagation delay nA to nY; see Figure 7
[2]
V
CC
= 0.8 V - 37.4 - - - - ns
V
CC
= 1.1 V to 1.3 V 4.8 9.5 19.0 4.4 21.6 24.0 ns
V
CC
= 1.4 V to 1.6 V 4.0 6.7 10.8 3.0 13.0 14.5 ns
V
CC
= 1.65 V to 1.95 V 2.9 5.6 8.4 2.6 10.3 11.5 ns
V
CC
= 2.3 V to 2.7 V 2.7 4.8 6.3 2.5 7.8 8.7 ns
V
CC
= 3.0 V to 3.6 V 2.7 4.6 5.8 2.5 7.0 8.3 ns
t
en
enable time 1OE to 1Y; see Figure 8
[3]
V
CC
= 0.8 V - 88.9 - - - - ns
V
CC
= 1.1 V to 1.3 V 5.2 9.9 19.8 4.8 22.8 25.3 ns
V
CC
= 1.4 V to 1.6 V 4.0 6.8 10.8 3.1 12.6 14.1 ns
V
CC
= 1.65 V to 1.95 V 3.0 5.6 8.5 2.8 10.2 11.3 ns
V
CC
= 2.3 V to 2.7 V 2.7 4.8 6.5 2.6 7.8 8.8 ns
V
CC
= 3.0 V to 3.6 V 2.7 4.6 6.0 2.6 6.9 7.7 ns
2OE to 2Y; see Figure 9
[3]
V
CC
= 0.8 V - 90.6 - - - - ns
V
CC
= 1.1 V to 1.3 V 4.7 10.0 20.4 4.3 22.0 22.0 ns
V
CC
= 1.4 V to 1.6 V 3.0 6.9 11.3 3.7 12.0 12.5 ns
V
CC
= 1.65 V to 1.95 V 2.6 5.6 8.6 3.2 9.5 10.1 ns
V
CC
= 2.3 V to 2.7 V 2.3 4.5 6.3 2.9 6.8 7.3 ns
V
CC
= 3.0 V to 3.6 V 2.2 4.2 5.8 2.7 6.4 6.7 ns
t
dis
disable time 1OE to 1Y; see Figure 8
[4]
V
CC
= 0.8 V - 49.9 - - - - ns
V
CC
= 1.1 V to 1.3 V 6.0 9.9 13.3 4.8 14.8 16.5 ns
V
CC
= 1.4 V to 1.6 V 4.4 7.7 9.6 3.1 10.7 12.1 ns
V
CC
= 1.65 V to 1.95 V 5.1 8.7 11.1 2.8 12.4 13.8 ns
V
CC
= 2.3 V to 2.7 V 3.6 6.2 7.4 2.6 8.6 9.6 ns
V
CC
= 3.0 V to 3.6 V 5.2 8.7 10.5 2.6 10.8 13.1 ns
2OE to 2Y; see Figure 9
[4]
V
CC
= 0.8 V - 51.6 - - - - ns
V
CC
= 1.1 V to 1.3 V 6.0 9.8 13.6 4.7 14.3 14.4 ns
V
CC
= 1.4 V to 1.6 V 4.5 7.7 10.5 3.0 10.7 11.0 ns
V
CC
= 1.65 V to 1.95 V 5.2 8.8 11.4 2.6 11.5 11.6 ns
V
CC
= 2.3 V to 2.7 V 3.9 6.4 7.4 2.3 9.0 10.2 ns
V
CC
= 3.0 V to 3.6 V 5.5 9.0 10.7 2.2 10.8 12.0 ns
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
(85 C)
Max
(125 C)
74AUP2G241 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 11 February 2013 13 of 26
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] t
en
is the same as t
PZH
and t
PZL
.
[4] t
dis
is the same as t
PHZ
and t
PLZ
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
12. Waveforms
C
L
= 5 pF, 10 pF, 15 pF and 30 pF
C
PD
power dissipation
capacitance
f = 1 MHz; V
I
= GND to V
CC
[5]
V
CC
= 0.8 V - 2.8 - - - - pF
V
CC
= 1.1 V to 1.3 V - 2.8 - - - - pF
V
CC
= 1.4 V to 1.6 V - 3.0 - - - - pF
V
CC
= 1.65 V to 1.95 V - 3.0 - - - - pF
V
CC
= 2.3 V to 2.7 V - 3.7 - - - - pF
V
CC
= 3.0 V to 3.6 V - 4.2 - - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
(85 C)
Max
(125 C)
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7. The data input (nA) to output (nY) propagation delays
mna230
t
PHL
t
PLH
V
M
V
M
nA input
nY output
GND
V
I
V
OH
V
OL
Table 9. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V 0.5 V
CC
0.5 V
CC
V
CC
3.0 ns
74AUP2G241 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 11 February 2013 14 of 26
NXP Semiconductors
74AUP2G241
Low-power dual buffer/line driver; 3-state
Measurement points are given in Table 10.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. 3-state enable and disable times
001aaa411
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
1OE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
V
OH
− 0.3 V
V
OL
+ 0.3 V
Measurement points are given in Table 10.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. 3-state enable and disable times
001aaa410
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
OH
− 0.3 V
V
OL
+ 0.3 V
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
2OE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 10. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
V
X
V
Y
0.8 V to 1.6 V 0.5 V
CC
0.5 V
CC
V
OL
0.1 V V
OH
0.1 V
1.65 V to 2.7 V 0.5 V
CC
0.5 V
CC
V
OL
0.15 V V
OH
0.15 V
3.0 V to 3.6 V 0.5 V
CC
0.5 V
CC
V
OL
0.3 V V
OH
0.3 V
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74AUP2G241GS,115

Mfr. #:
Buy 74AUP2G241GS,115
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers 3.6 V XSON8
Lifecycle:
New from this manufacturer.
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