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ISL6420IAZ-TK

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
13
FN9151.5
February 13, 2008
A small ceramic capacitor should be placed in parallel with
R
OCSET
to smooth the voltage across R
OCSET
in the
presence of switching noise on the input voltage.
Voltage Margining
The ISL6420 has a voltage margining mode that can be
used for system testing. The voltage margining percentage
is resistor selectable up to ±10%. The voltage margining
mode can be enabled by connecting a margining set resistor
from VMSET/MODE pin to ground and using the control pins
GPIO1/REFIN and GPIO2 to toggle between positive and
negative margining (Refer to Table 2). With voltage
margining enabled, the VMSET resistor to ground sets a
current, which is switched to the FB pin. The current will be
equal to 2.468V divided by the value of the external resistor
tied to the VMSET/MODE pin.
The power supply output increases when GPIO2 is HIGH
and decreases when GPIO1/REFIN is HIGH. The amount
that the output voltage of the power supply changes with
voltage margining, will be equal to 2.468V times the ratio of
the external feedback resistor and the external resistor tied
to VMSET/MODE pin. Figure 9 shows the positive and
negative margining for a 3.3V output, using a 20.5kΩ
feedback resistor and using various VMSET resistor values.
The slew time of the current is set by an external capacitor
on the CDEL pin, which is charged and discharged with a
100μA current source. The change in voltage on the
capacitor is 2.5V. This same capacitor is used to set the
PGOOD active delay after soft-start. When PGOOD is low,
the internal PGOOD circuitry uses the capacitor and when
PGOOD is high the voltage margining circuit uses the
capacitor. The slew time for voltage margining can be in the
range of 300µs to 2ms.
External Reference/DDR Supply
The voltage margining can be disabled by connecting the
VMSET/MODE to VCC5. In this mode the chip can be
configured to work with an external reference input and
provide a buffered reference output.
If VMSET/MODE pin and the GPIO1/REFIN pin are both tied
to VCC5, then the internal 0.6V reference is used as the
error amplifier non-inverting input. The buffered reference
output on REFOUT will be 0.6V ±0.01V, capable of sourcing
20mA and sinking up to 50µA current with a 2.2µF capacitor
connected to the REFOUT pin.
If VMSET/MODE pin is tied to high but GPIO1/REFIN is
connected to external voltage source between 0.6V to 1.25V,
then this external voltage is used as the reference voltage at
the positive input of the error amplifier. The buffered
reference output on REFOUT will be Vrefin ±0.01V, capable
of sourcing 20mA and sinking up to 50µA current with a
2.2µF capacitor on the REFOUT pin.
Power Good
The PGOOD pin can be used to monitor the status of the
output voltage. PGOOD will be true (open drain) when the
FB pin is within ±10% of the reference and the ENSS pin has
completed its soft-start ramp.
Additionally, a capacitor on the CDEL pin will set a delay for
the PGOOD signal. After the ENSS pin completes its soft-
start ramp, a 2µA current begins charging the CDEL
I
VM
2.468V
R
VMSET
------------------------
=
(EQ. 2)
V
VM
Δ 2.468V
R
FB
R
VMSET
------------------------
=
(EQ. 3)
2.8
2.9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
150 175 200 225 250 275 300 325 350 375 400
RVMSET (kΩ)
V
OUT
(V)
3.0
FIGURE 10. VOLTAGE MARGINING vs VMSET RESISTANCE
V
OUT
100m/DIV
V
OUT
100mV/DIV
2ms/DIV
FIGURE 11. VOLTAGE MARGINING SLEW TIME
ISL6420
14
FN9151.5
February 13, 2008
capacitor to 2.5V. The capacitor will be quickly discharged
before PGOOD goes high. The programmable delay can be
used to sequence multiple converters or as a LOW-true
reset signal.
If the voltage on the FB pin exceeds ±10% of the reference,
then PGOOD will go low after 3µs of noise filtering.
Over-Temperature Protection
The IC is protected against over temperature conditions.
When the junction temperature exceeds +150°C, the PWM
shuts off. Normal operation is resumed when the junction
temperature is cooled down to +130°C.
Shutdown
When ENSS pin is below 1V, the regulator is disabled with
the PWM output drivers tri-stated. When disabled, the IC
power will be reduced.
Under-Voltage
If the voltage on the FB pin is less than 15% of the reference
voltage for 8 consecutive PWM cycles, then the circuit enters
into soft-start hiccup mode. This mode is identical to the
overcurrent hiccup mode.
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage by
15%, the lower gate driver is turned on continuously to
discharge the output voltage. If the overvoltage condition
continues for 32 consecutive PWM cycles, then the chip is
turned off with the gate drivers tri-stated. The voltage on the
FB pin will fall and reach the 15% undervoltage threshold.
After 8 clock cycles, the chip will enter soft-start hiccup
mode. This mode is identical to the overcurrent hiccup
mode.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
Figure 12 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 12 should be located as close
together as possible. Please note that the capacitors C
IN
and C
O
each represent numerous physical capacitors.
Locate the ISL6420 within 3 inches of the MOSFETs, Q1 and
Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6420 must be sized to handle up to
1A peak current.
Figure 13 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the ENSS PIN and locate the capacitor, C
ss
close to the ENSS pin because the internal current source is
only 30µA. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 14 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
E/A
) is compared with the
FIGURE 12. PGOOD DELAY
GND
L
O
C
O
LGATE
UGATE
PHASE
Q1
Q2
D2
FIGURE 13. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
V
IN
V
OUT
RETURN
ISL6420
C
IN
LOAD
ISL6420
15
FN9151.5
February 13, 2008
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output filter
(L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of Vout/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage ΔV
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6420) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180
o
. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 14. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole
(~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 15 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak do to the high Q factor of the output
filter and is not shown in Figure 15. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier. The Loop Gain is
constructed on the log-log graph of Figure 15 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
FIGURE 14. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+5V
ISL6420
ENSS
GND
VCC
BOOT
D1
L
O
C
O
V
OUT
LOAD
Q1
Q2
PHASE
+V
IN
C
BOOT
C
VCC
C
SS
FIGURE 15. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
ΔV
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
-
REF
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6420
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
Z
FB
+
F
LC
1
2π L
O
C
O
••
---------------------------------------
=
(EQ. 4)
F
ESR
1
2π ESR C
O
•()•
---------------------------------------------
=
(EQ. 5)
F
Z1
1
2π R• 2C1•
----------------------------------
=
(EQ. 6)
F
P1
1
2π R2•
C1 C2•
C1 C2+
----------------------
⎝⎠
⎛⎞
•
------------------------------------------------------ -
=
(EQ. 7)
F
Z2
1
2π R1 R3+()C3••
------------------------------------------------------
=
(EQ. 8)
F
P2
=
1
2π R3 C3••
----------------------------------
(EQ. 9)
ISL6420
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ISL6420IAZ-TK

Mfr. #:
Buy ISL6420IAZ-TK
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers SYNC BUCK PWM CONT 5V-16V INPUT 20LD
Lifecycle:
New from this manufacturer.
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