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NJG1524APC1-TE1

P1-P3P4-P6P7-P8
NJG1524APC1
- 1 -
DPDT SWITCH GaAs MMIC
nGENERAL DESCRIPTION nPACKAGE OUTLINE
NJG1524APC1 is a DPDT switch GaAs MMIC.
The two same switches are merged into one package
and functionally linked. It is useful for switching two
circuits in-line.
Each switches feature very low loss, high isolation
and wide frequency coverage from 50MHz to 3GHz at
low control voltage of 2.5V.
The ultra small & thin FFP16-C1package is adopted.
nFEATURES
lSingle low voltage control +2.5~+6.5V
lLow insertion loss 0.3dB typ.@f=1GHz, P
IN
=0dBm, each switch
0.5dB typ.@f=2GHz, P
IN
=0dBm, each switch
lHigh isolation 42dB typ. @f=2GHz,PC1-PC2
27dB typ.@f=2GHz, PC1-PA1 PC1-PA2, PC2-PB1,
PC2-PB2, PA1-PA2, PB1-PB2
lHanding power 20dBm max. @f=2GHz, V
CTL
=2.7V
lLow current consumption 16uA typ.@f=2GHz, P
IN
=10dBm
lUltra small & thin package FFP16-C1 (Package size: 2.5x2.5x0.85mm)
nPIN CONFIGURATION
nTRUTH TABLE
VCTL1 H L
VCTL2 L H
PC1 – PA1
PC2 – PB1
ON OFF
PC1 – PA2
PC2 – PB2
OFF ON
FFP16 Type
(Top View)
NJG1524APC1
“H”=V
CTL (H)
, “L”=V
CTL (L)
Pin Connection
1.GND 9.GND
2.GND
10.PC1
3.PC2
11.GND
4.GND 12.GND
5.PB1 13.PA2
6.NC 14.VCTL1
7.VCTL1 15.VCTL2
8.PA1 16.PB2
NOTE: Please note that any information on this catalog will be subject to change.
1
2
1
3
3
4
5
6
7
8
9
10
11
12
NJG1524APC1
- 2 -
nABSOLUTE MAXIMUM RATINGS
(T
a
=25°C)
PARAMETER SYMBOL
CONDITIONS RATINGS UNITS
Input Power P
IN
V
CTL (L)
=0V, V
CTL (H)
=2.7V
28 dBm
Control voltage V
CTL
V
CTL (H)
- V
CTL (L)
7.5 V
Power Dissipation P
D
400 mW
Operating Temp. T
opr
-40~+85 °C
Storage Temp. T
stg
-55~+125 °C
nELECTRACAL CHARACTERISTICS (EACH SWITCH)
(V
CTL (L)
=0V, V
CTL (H)
=2.7V, Z
S
=Z
O
=50Ω, T
a
=25°C)
PARAMETER SYMBOL
CONDITIONS MIN TYP MAX UNITS
Operating voltage (L)
V
CTL (L)
-0.2 0 0.2 V
Operating voltage (H)
V
CTL (H)
2.5 2.7 6.5 V
Control Current I
CTL
f=2GHz, P
IN
=10dBm - 16 28 uA
Insertion loss1 Loss1
PC1-PA1, PC1-PA2,
PC2-PB1, PC2-PB2 ON,
f=1GHz, P
IN
=0dBm
- 0.3 0.6 dB
Insertion loss2 Loss2
PC1-PA1, PC1-PA2,
PC2-PB1, PC2-PB2 ON,
f=2GHz, P
IN
=0dBm
- 0.5 0.8 dB
Isolation1 ISL1
PC1-PA1, PC1-PA2,
PC2-PB1, PC2-PB2 OFF,
f=1GHz, P
IN
=0dBm
25.5 27 - dB
Isolation2 ISL2
PC1-PA1, PC1-PA2,
PC2-PB1, PC2-PB2 OFF,
f=2GHz, P
IN
=0dBm
25 27 - dB
Isolation3 ISL3
PA1, PA2, PB1, PB2 port
50Ω terminal, PC1-PC2
port, f=2GHz, P
IN
=0dBm
VCTL1=2.7V
39 42 - dB
Pin at 1dB
compression point
P
-1dB
f=2GHz 20 23 - dBm
VSWR (PC, P1, P2) VSWR f=0.05~2GHz, ON State - 1.3 1.6
Switch time T
SW
f=0.05~2.5GHz - 40 60 ns
NJG1524APC1
- 3 -
nTERMINAL INFORMATION
No. SYMBOL
DESCRIPTIONS
3 PC2
Common RF port C2. In order to block the DC bias voltage of internal
circuit, an external capacitor is required.
5 PB1
RF port B1. This port is connected with PC1 port by controlling
VCTL2 to -0.2~+0.2V and VCTL1 to 2.5~6.5V. In order to block the
DC bias voltage of internal circuit, an external capacitor is required.
6 NC No connected terminal.
7 VCTL1
Control port 1. The voltage of this port controls PC1 to PA1/PA2 and
PC2 to PB1/PB2 state. The ‘ON’ and ‘OFF’ state is toggled by
controlling voltage of this terminal to high-state (2.5~6.5V) or
low-state (-0.2~+0.2V). The voltage of VCTL2 should be set to
opposite state. The bypass capacitor should be connected with GND
as close as possible for excellent RF performance.
8 PA1
RF port A1. This port is connected with PC1 port by controlling
VCTL2 to -0.2~+0.2V and VCTL1 to 2.5~6.5V. In order to block the
DC bias voltage of internal circuit, an external capacitor is required.
10 PC1
Common RF port C1. In order to block the DC bias voltage of internal
circuit, an external capacitor is required.
13 PA2
RF port A2. This port is connected with PC1 port by controlling V
CTL
(L)
to -0.2~+0.2V and V
CTL (H)
to 2.5~6.5V. In order to block the DC
bias voltage of internal circuit, an external capacitor is required.
14 VCTL1
Control port 1. The voltage of this port controls PC1 to PA1/PA2 and
PC2 to PB1/PB2 state. The ‘ON’ and ‘OFF’ state is toggled by
controlling voltage of this terminal to high-state (2.5~6.5V) or
low-state (-0.2~+0.2V). The voltage of VCTL2 should be set to
opposite state. The bypass capacitor should be connected with GND
as close as possible for excellent RF performance.
15 VCTL2
Control port 2. The voltage of this port controls PC1 to PA1/PA2 and
PC2 to PB1/PB2 state. The ‘ON’ and ‘OFF’ state is toggled by
controlling voltage of this terminal to high-state (2.5~6.5V) or
low-state (-0.2~+0.2V). The voltage of VCTL1 should be set to
opposite state. The bypass capacitor should be connected with GND
as close as possible for excellent RF performance.
16 PB2
RF port B2. This port is connected with PC2 port by controlling
VCTL1 to -0.2~+0.2V and VCTL2 to 2.5~6.5V. In order to block the
DC bias voltage of internal circuit, an external capacitor is required.
1, 2, 4, 9,
11, 12
GND
Ground terminal. Please connect this terminal with ground plane as
close as possible for excellent RF performance.
P1-P3P4-P6P7-P8

NJG1524APC1-TE1

Mfr. #:
Buy NJG1524APC1-TE1
Manufacturer:
NJR (New Japan Radio)
Description:
RF Switch ICs DPDT Switch
Lifecycle:
New from this manufacturer.
Delivery:
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