Write Function
MC33690 Standalone Tag Reader Circuit, Rev. 5
Freescale Semiconductor 7
reference is the falling edge of the driving signal TD1, this leads to a sampling time phase ranging from −78.75° to 90° with
discrete steps of 11.25°. After reset condition, the sampling time phase is +11.25°.
The antenna phase shift evaluation is only done after each wake-up command or after reset. This is necessary to obtain the best
demodulator performances.
To ensure a fast demodulator settling time after wake-up, reset, or a write sequence, the external capacitor CEXT is preloaded
at its working voltage. This preset occurs 256µs after switching the antenna drivers on and its duration is 128µs. After wake-up
or reset, the preset has the same duration, but begins 518µs after clock settling. After power on reset, VSUP must meet the
minimum specified value, enabling the nominal operation of VDD, before the start of the preset. Otherwise, the preset must be
done through a standby/wake-up sequence.
3 Write Function
Whatever the selected configuration (see Section 6, “Communication Modes Description”), the write function is achieved by
switching on/off the output drivers TD1/2. After the drivers have been set in high impedance, the load current flows alternatively
through the internal diodes to VSS and to VDD (see Figure 3).
Figure 3. Current Flow When Buffers are Switched Off
4 Voltage Regulator
The low dropout voltage regulator provides a regulated 5V supply for the internal circuitry. It can also supply external
peripherals or sensors. The input supply voltage ranges from 5.5V to over 40V.
This voltage regulator uses a series combination of high voltage LDMOS and low voltage PMOS transistors to provide
regulation. An external low ESR capacitor is required for the regulator stability.
The maximum average current is limited by the power dissipation capability of the SO 20 package. This limitation can be
overcome by connecting an external N channel MOS parallel with the internal LDMOS. The threshold voltage of this transistor
must be lower than the one of the internal LDMOS (1.95V typ.) to prevent the current from flowing into the LDMOS. Its
breakdown voltage must be higher than the maximum supply voltage.
A low-voltage reset function monitors the VDD output. An internal 10µA pull-up current source allows, when an external
capacitor is connected between LVR and GND, to generate delays at power up (5ms typ. with C
Reset
=22nF). The LVR pin is
C
A
L
A
R
1
R
A
TD1
VDD
TD2
VDD
I
LOAD
