OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SAA7105E/V1/G,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
2004 Mar 04 31
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 31 Subaddress 29H
Table 32 Subaddresses 2AH to 2CH
Table 33 Subaddress 2DH
DATA BYTE
LOGIC
LEVEL
DESCRIPTION REMARKS
SRES 0 pin TTX_SRES accepts a teletext bit
stream (TTX)
default after reset
1 pin TTX_SRES accepts a sync reset input
(SRES)
a HIGH impulse resets synchronization of the
encoder (first field, first line)
BE − ending point of burst in clock cycles PAL: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to LOW
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
CG − LSBs of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.
CGEN 0 copy generation data output is disabled; default after reset
1 copy generation data output is enabled
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
VBSEN 0 pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS
signal (CVBSEN1 = 1)
1 pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset
CVBSEN1 0 pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal;
default after reset
1 pin GREEN_VBS_CVBS provides a CVBS signal
CVBSEN0 0 pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (C
B
) signal
1 pin BLUE_CB_CVBS provides a CVBS signal; default after reset
CEN 0 pin RED_CR_C_CVBS provides a component RED (R) or colour difference RED (C
R
) signal
1 pin RED_CR_C_CVBS provides a chrominance signal (C) as modulated subcarrier for
S-video; default after reset
ENCOFF 0 encoder is active; default after reset
1 encoder bypass, DACs are provided with RGB signal after cursor insertion block
CLK2EN 0 pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ)
1 pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default
after reset
CVBSEN2 0 pin RED_CR_C_CVBS provides a signal according to CEN; default after reset
1 pin RED_CR_C_CVBS provides a CVBS signal
2004 Mar 04 32
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 34 Subaddress 37H
Table 35 Logic levels and function of YFIL
Table 36 Subaddresses 38H and 39H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
YUPSC 0 normal operation of the vertical scaler; default after reset
1 vertical upscaling is enabled
YFIL − controls the vertical interpolation filter, see Table 35; the filter is not available if
YUPSC = 1
CZOOM 0 normal operation of the cursor generator; default after reset
1 the cursor will be zoomed by a factor of 2 in both directions
IGAIN 0 expected input level swing is 16 to 235 (8-bit RGB); default after reset
1 expected input level swing is 0 to 255 (8-bit RGB)
XINT 0 no horizontal interpolation filter; default after reset
1 interpolation filter for horizontal upscaling is active
DATA BYTE
DESCRIPTION
YFIL1 YFIL0
0 0 no filter active; default after reset
0 1 filter is inserted before vertical scaling
1 0 filter is inserted after vertical scaling; YSKIP should be logic 0
1 1 reserved
DATA BYTE DESCRIPTION
GY4 to GY0 Gain luminance of RGB (C
R
, Yand C
B
) output, ranging from (1 −
16
⁄
32
)to(1+
15
⁄
32
).
Suggested nominal value = 0, depending on external application.
GCD4 to GCD0 Gain colour difference of RGB (C
R
, Yand C
B
) output, ranging from
(1 −
16
⁄
32
)to(1+
15
⁄
32
). Suggested nominal value = 0, depending on external
application.
2004 Mar 04 33
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 37 Subaddress 3AH
Table 38 Subaddress 54H
Table 39 Subaddresses 55H to 59H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
CBENB 0 data from input ports is encoded
1 colour bar with fixed colours is encoded
SYNTV 0 in slave mode, the encoder is only synchronized at the beginning of an odd field; default
after reset
1 in slave mode, the encoder receives a vertical sync signal
SYMP 0 horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default
after reset
1 horizontal and vertical trigger is decoded out of
“ITU-R BT.656”
compatible data at PD port
DEMOFF 0 Y-C
B
-C
R
to RGB dematrix is active; default after reset
1Y-C
B
-C
R
to RGB dematrix is bypassed
CSYNC 0 pin HSM_CSYNC provides a horizontal sync for non-interlaced VGA components output
(at PIXCLK)
1 pin HSM_CSYNC provides a composite sync for interlaced components output (at XTAL
clock)
Y2C 0 input luminance data is twos complement from PD input port
1 input luminance data is straight binary from PD input port; default after reset
UV2C 0 input colour difference data is twos complement from PD input port
1 input colour difference data is straight binary from PD input port; default after reset
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
VPSEN 0 video programming system data insertion is disabled; default after reset
1 video programming system data insertion in line 16 is enabled
GPVAL 0 pin VSM provides a LOW level if GPEN = 1
1 pin VSM provides a HIGH level if GPEN = 1
GPEN 0 pin VSM provides a vertical sync for a monitor; default after reset
1 pin VSM provides a constant signal according to GPVAL
EDGE 0 input data is sampled with inverse clock edges
1 input data is sampled with the clock edges specified in Tables 9 to 14; default after reset
SLOT 0 normal assignment of the input data to the clock edge; default after reset
1 correct time misalignment due to inverted assignment of input data to the clock edge
DATA BYTE DESCRIPTION REMARKS
VPS5 fifth byte of video programming system data in line 16; LSB first; all other bytes are not
relevant for VPS
VPS11 eleventh byte of video programming system data
VPS12 twelfth byte of video programming system data
VPS13 thirteenth byte of video programming system data
VPS14 fourteenth byte of video programming system data
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

SAA7105E/V1/G,518

Mfr. #:
Buy SAA7105E/V1/G,518
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 156LBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet