MT4KTF25664AZ-1G9P1

DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.
Table 9: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-2G1 -093
-1G9 -107
-1G6 -125
-1G4 -15E
-1G1 -187E
-1G0 -187
-80C -25E
-80B -25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
2GB (x64, SR) 240-Pin DDR3L UDIMM
DRAM Operating Conditions
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ktf4c256x64az.pdf - Rev. E 12/15 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
I
DD
Specifications
Table 10: DDR3 I
DD
Specifications and Conditions – 2GB (Die Revision P)
Values are for the MT41K256M16 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb (256 Meg
x 16) component data sheet
Parameter Symbol 1866 1600 Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE I
DD0
128 128 mA
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE I
DD1
184 180 mA
Precharge power-down current: Slow exit I
DD2P0
48 48 mA
Precharge power-down current: Fast exit I
DD2P1
48 48 mA
Precharge quiet standby current I
DD2Q
60 60 mA
Precharge standby current I
DD2N
68 68 mA
Precharge standby ODT current I
DD2NT
92 92 mA
Active power-down current I
DD3P
68 68 mA
Active standby current I
DD3N
92 88 mA
Burst read operating current I
DD4R
416 368 mA
Burst write operating current I
DD4W
468 424 mA
Refresh current I
DD5B
624 624 mA
Self refresh temperature current: MAX T
C
= 85°C I
DD6
60 60 mA
Self refresh temperature current (SRT-enabled): MAX T
C
= 95°C I
DD6ET
92 92 mA
All banks interleaved read current I
DD7
588 528 mA
Reset current I
DD8
56 56 mA
2GB (x64, SR) 240-Pin DDR3L UDIMM
I
DD
Specifications
PDF: 09005aef84cae8ad
ktf4c256x64az.pdf - Rev. E 12/15 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Serial Presence-Detect EEPROM
For the latest SPD data, refer to Micron's SPD page: micron.com/spd.
Table 11: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
DDSPD
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
3.0 3.6 V
Input low voltage: Logic 0; All inputs V
IL
–0.45 V
DDSPD
x 0.3 V
Input high voltage: Logic 1; All inputs V
IH
V
DDSPD
x 0.7 V
DDSPD
+ 1.0 V
Output low voltage: I
OUT
= 3mA V
OL
0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 2.0 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 2.0 µA
Table 12: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
Clock frequency
t
SCL 10 400 kHz
Clock pulse width HIGH time
t
HIGH 0.6 µs
Clock pulse width LOW time
t
LOW 1.3 µs
SDA rise time
t
R 300 µs 1
SDA fall time
t
F 20 300 ns 1
Data-in setup time
t
SU:DAT 100 ns
Data-in hold time
t
HD:DI 0 µs
Data-out hold time
t
HD:DAT 200 900 ns
Data out access time from SCL LOW
t
AA:DAT 0.2 0.9 µs 2
Start condition setup time
t
SU:STA 0.6 µs 3
Start condition hold time
t
HD:STA 0.6 µs
Stop condition setup time
t
SU:STO 0.6 µs
Time the bus must be free before a new transition can
start
t
BUF 1.3 µs
WRITE time
t
W 10 ms
Notes:
1. Guaranteed by design and characterization, not necessarily tested.
2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-
ing edge of SCL and the falling or rising edge of SDA.
3. For a restart condition, or following a WRITE cycle.
2GB (x64, SR) 240-Pin DDR3L UDIMM
Serial Presence-Detect EEPROM
PDF: 09005aef84cae8ad
ktf4c256x64az.pdf - Rev. E 12/15 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.

MT4KTF25664AZ-1G9P1

Mfr. #:
Manufacturer:
Micron
Description:
Memory Modules DDR3 2GB UDIMM
Lifecycle:
New from this manufacturer.
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