REV.
ADP3300
–6–
THEORY OF OPERATION
The new anyCAP LDO ADP3300 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and
a second resistor divider (R3 and R4) to the input of an amplifier.
g
m
PTAT
V
OS
R4
R3
D1
R1
ATTENUATION
(V
BANDGAP
/V
OUT
)
R2
(a)
COMPENSATION
CAPACITOR
NONINVERTING
WIDEBAND
DRIVER
Q1
INPUT
C
LOAD
OUTPUT
ADP3300
R
LOAD
PTAT
CURRENT
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complimentary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility
on the trade-off of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1 and a second divider consisting
of R3 and R4, the values are chosen to produce a temperature
stable output. This unique arrangement specifically corrects for
the loading of the divider so that the error resulting from base
current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value, required to keep conventional
LDOs stable, changes depending on load and temperature.
These ESR limitations make designing with LDOs more diffi-
cult because of their unclear specifications and extreme variations
over temperature.
This is no longer true with the ADP3300 anyCAP LDO. It can
be used with virtually any capacitor, with no constraint on the
minimum ESR. The innovative design allows the circuit to be
stable with just a small 0.47 µF capacitor on the output. Addi-
tional advantages of the pole splitting scheme include superior line
noise rejection and very high regulator gain, which leads to excel-
lent line and load regulation. An impressive ±1.4% accuracy is
guaranteed over line, load and temperature.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard solu-
tions that give warning after the output has lost regulation,
the ADP3300 provides improved system performance by enabling
the ERR pin to give warning before the device loses regulation.
As the chip’s temperature rises above 165°C, the circuit activates a
soft thermal shutdown, indicated by a signal low on the ERR
pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main
divider network (a) is made available at the noise reduction (NR)
pin, which can be bypassed with a small capacitor (10 nF–100 nF).
APPLICATION INFORMATION
Capacitor Selection: anyCAP
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3300 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. The ADP3300 is
stable with extremely low ESR capacitors (ESR ≈ 0), such as
multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not
required; however, for applications where the input source is high
impedance or far from the input pins, a bypass capacitor is recom-
mended. Connecting a 0.47 µF capacitor from the input to
ground reduces the circuit’s sensitivity to PC board layout. If a
bigger output capacitor is used, the input capacitor should be 1 µF
minimum.
Noise Reduction
A noise reduction capacitor (C
NR
) can be used to further reduce
the noise by 6 dB–10 dB (Figure 3). Low leakage capacitors in
the 10 nF–100 nF range provide the best performance. For load
current less than 200 µA, a 4.7 µF output capacitor provides the
lowest noise and the best overall performance. Since the noise
reduction pin (NR) is internally connected to a high impedance
node, any connection to this node should be carefully done to
avoid noise pickup from external sources. The pad connected to
this pin should be as small as possible. Long PC board traces
are not recommended.
IN
OUT
ERR
GND
ADP3300-5
NR
ON
OFF
SD
C2
4.7F
330k⍀
E
OUT
C1
1.0F
V
OUT
= 5V
V
IN
C
NR
10nF
+
+
Figure 3. Noise Reduction Circuit
