NCV8184
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60
70
80
90
100
110
120
130
140
150
0 100 200 300 400 500 600 700
1.0 oz Cu
2.0 oz Cu
Figure 29. SOIC–8 Exposed Pad, θ
JA
as a Function of
the Pad Copper Area, Board Material FR4
q
JA
(°C/W)
T
J
= 25°C
COPPER HEAT SPREADER AREA (mm
2
)
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
Figure 30. SOIC–8 Exposed Pad Thermal Duty Cycle
Curves on 1.0 in Spreader Test Board, 1.0 oz Cu
50% Duty Cycle
20%
Single Pulse
10%
5%
2%
1%
(1.0 in pad PCB) Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
Duty Cycle, D =
t
1
t
2
P
DM
Notes:
t
1
t
2
R(t) (°C/W)
0.1
1
10
100
1000
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
Figure 31. SOIC–8 Exposed Pad Single Pulse Heating Curve
Cu Area 645 mm
2
Cu Area 100 mm
2
R(t) (°C/W)
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PACKAGE THERMAL DATA
Parameter
Conditions
Typical Value
Units
DPAK 5LEAD Package
100 mm
2
Spreader Board 645 mm
2
Spreader Board
1 oz 2 oz 1 oz 2 oz
JunctiontoBoard-top (YJB, Y
JB
)
18 18 17 16 °C/W
JunctiontoPin 3 (tab) (YJL3, Y
JL3
)
16 16 16 16 °C/W
JunctiontoAmbient (R
q
JA
, q
JA
)
87 77 62 55 °C/W
Package construction
Without mold compound
Figure 32. PCB Layout and Package Construction for Simulation
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Table 3. DPAK 5LEAD THERMAL RC NETWORK MODELS*
Drain Copper Area (1 oz thick) 100 mm
2
645 mm
2
100 mm
2
645 mm
2
(SPICE Deck Format) Cauer Network Foster Network
100 mm
2
645 mm
2
Units Tau Tau Units
C_C1 Junction Gnd 0.0000016 0.0000016 Ws/C 1.00E-06 1.00E-06 sec
C_C2 node1 Gnd 0.0000060 0.0000060 Ws/C 1.00E-05 1.00E-05 sec
C_C3 node2 Gnd 0.0000177 0.0000177 Ws/C 1.00E-04 1.00E-04 sec
C_C4 node3 Gnd 0.0001586 0.0001587 Ws/C 1.76E-04 1.76E-04 sec
C_C5 node4 Gnd 0.0001927 0.0001931 Ws/C 0.0010 0.0010 sec
C_C6 node5 Gnd 0.0056684 0.0058019 Ws/C 0.030 0.030 sec
C_C7 node6 Gnd 0.0832719 0.1225791 Ws/C 0.285 0.299 sec
C_C8 node7 Gnd 0.1125429 0.3555671 Ws/C 3.00 3.00 sec
C_C9 node8 Gnd 0.5161495 1.2959188 Ws/C 9.03 11.80 sec
C_C10 node9 Gnd 1.4600223 1.8396650 Ws/C 55.2 79.0 sec
100 mm
2
645 mm
2
R’s R’s
R_R1 Junction node1 0.8287213 0.8287120 °C/W 0.490938 0.490938 °C/W
R_R2 node1 node2 1.9304163 1.9303119 °C/W 1.061544 1.061544 °C/W
R_R3 node2 node3 4.7751915 4.7743247 °C/W 3.356895 3.356895 °C/W
R_R4 node3 node4 2.3736457 2.3705112 °C/W 1.606314 1.606314 °C/W
R_R5 node4 node5 2.0679537 2.0623650 °C/W 5.00 5.00 °C/W
R_R6 node5 node6 5.3364094 5.1102633 °C/W 5.00 5.00 °C/W
R_R7 node6 node7 6.0331860 3.2428679 °C/W 2.00 2.00 °C/W
R_R8 node7 node8 22.7616126 8.6995800 °C/W 9.147005 5.071663 °C/W
R_R9 node8 node9 17.9894079 16.1165074 °C/W 17.23178 3.646957 °C/W
R_R10 node9 gnd 22.7199543 16.7871407 °C/W 41.92202 34.68827 °C/W
*Bold face items in the tables above represent the package without the external thermal system.
The Cauer networks generally have physical significance
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Cauer
networks can be easily implemented using circuit simulating
tools, whereas Foster networks may be more easily
implemented using mathematical tools (for instance, in a
spreadsheet program), according to the following formula:
R(t) +
n
S
i + 1
R
i
ǒ
1e
tń tau
i
Ǔ

NCV8184DTRK

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 70mA Tracking
Lifecycle:
New from this manufacturer.
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