© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 8
1 Publication Order Number:
MC10EP16VC/D
MC100EP16VC
3.3V / 5V ECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN
input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG
outputs.
When the EN
signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
EN
goes HIGH, it will force the Q
HG
LOW and the Q
HG
HIGH on the
next negative transition of the data input. If the data input is LOW
when the EN
goes HIGH, the next data transition to a HIGH is ignored
and Q
HG
remains LOW and Q
HG
remains HIGH. The next positive
transition of the data input is not passed on to the data outputs under
these conditions. The Q
HG
and Q
HG
outputs remain in their disabled
state as long as the EN
input is held HIGH. The EN input has no
influence on the Q
output and the data input is passed on (inverted) to
this output whether EN
is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
The V
BB
/D pin is internally dedicated and available for differential
interconnect. V
BB
/D may rebias AC coupled inputs. When used,
decouple V
BB
/D and V
CC
via a 0.01 mF capacitor and limit current
sourcing or sinking to 1.5 mA. When not used, V
BB
/D should be left
open.
The 100 Series contains temperature compensation.
Features
• 310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
• Gain > 200
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range:
♦ V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
♦ V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Q
HG
Output Will Default LOW with D Inputs Open or at V
EE
• V
BB
Output
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
MARKING DIAGRAMS*
ALYWG
G
KP66
1
8
www.onsemi.com
KEP66
ALYW
G
1
8
3G MG
G
14
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
†
MC100EP16VCDG SOIC−8NB
(Pb-Free)
98 Units/Tube
MC100EP16VCDR2G SOIC−8NB
(Pb-Free)
2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EP16VCDTR2G 2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EP16VCDTG 100 Units/Tube
DFN−8
(Pb-Free)
MC100EP16VCMNR4G 1000/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
*For additional marking information, refer to
Application Note AND8002/D
.
SOIC−8NB
D SUFFIX
CASE
751−07
TSSOP−8
DT SUFFIX
CASE
948R−02
1
8
1
8
DFN−8
MN SUFFIX
CASE 506AA
