4
ICS9212-13
0272F—08/08/07
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Parameters S
mbol Min Max Uni
Supply Voltage VDD 3.135 3.465 V
Refclk Input cycle time t
CYCLE,I N
10 40 ns
Input cycle-to-cycle Jitter t
J,IN
- 250 ps
Input Duty cycle over 10k cycles
DC
IN
40% 60%
t
CYCLE
Input frequency of modulation F
m,in
30 33 kHz
Modulation index P
M,IN
0.25 0.5 %
Phase detector in
ut c
cle time at PDclk/M & S
nclk/N t
30 100 ns
Initial phase error at phase detector inputs T
err,init
-0.5 0.5 t
CYCLE,PD
Phase detector input duty cycle over 10k cycles D
CI N, PD
25% 75% t
CYCLE,PD
Input rise & fall times ( measured at 20%-80% of input voltage) for
PDCLK/M & SYNCLK/N
&REfCLK
T
IR
,T
IF
-1ns
Input capacitance at PDCLK/M,Synclk/N,&REFCLK C
IN,PD
-7pF
Input Capacitance matching at PCLK/M & SYNCLK/N DC
IN
PD
-0.5pF
Input capacitance at CMOS pins C
IN,CMOS
-10pF
Input (CMOS) signal low voltage V
IL
-0.3Vdd
Input (CMOS) signal high voltage V
IH
0.7 - Vdd
REFCLK input low voltage V
IL,R
- 0.3 Vddi,R
REFCLK input high voltage V
IH,
0.7 - Vddi,R
Input signal low voltage for PD inputs and STOP
V
IL
PD
- 0.3 Vddi,PD
Input signal high voltage for PD inputs and STOP V
IH,PD
0.7 - Vddi,PD
Input supply referance for REFCLK V
DD,IR
1.3 3.465 V
Input supply referance vfor PD inputs V
DDI , PD
1.3 3.465 V
Phase detector phase error for distributed loop measured at
PDCLK/M & SYNCLK/N(rising
t
ERR,PD
-100 100 ps
Cycle cycle time t
CYCLE
2.5 3.75 ns
Cycle-to-cycle jitter at Busclk/BUSCLKB (533 MHz) t
J
-40ps
Total jitter over 1 - 6 cycles (533MHz) t
J
-30ps
Phase aligner, phase step size (BSCLK/BUSCLKB) t
STEP
1-ps
PLL out put phase error when tracking SSC t
ERR, SSC
-100 100 ps
Out put crossing-point voltage V
X
1.3 1.8 V
Output voltage swing V
COS
0.4 0.6 V
Output high voltage V
H
-2V
Out put duty cycle over 10k cycle DC 40% 60% t
CYCLE
Output cycle -to-cycle duty cycle error
t
DC
ERR
-50ps
Output rise & fall times ( measured at 20%-80% of output voltage) t
CR
,t
CF
300 500 ps
Difference between rise and fall times on a single device(20%-80%) t
CR, CF
- 100 ps
Opearting Supply Current I
DD
150 mA
Electrical Characteristics-input/supply/Outputs
