ADP2291
Rev. A | Page 12 of 20
APPLICATION INFORMATION
SETTING THE MAXIMUM CHARGE CURRENT
The maximum charge current is set by choosing the proper
current sense resistor, R
S
, and the voltage on the ADJ input.
The charger nominally regulates its output current at the point
where the voltage across the current sense resistor V
IN
– V
CS
(defined as V
RS
) is 150 mV. This setpoint voltage can be adjusted
by pulling down on the ADJ input, which is internally attached
through a 100 k
pull-up resistor to 3 V. Each volt of pull-down
from 3 V reduces V
RS
by 67 mV during fast charge. A minimum
of 50 mV is reached when a 100 k
resistor is attached between
ADJ and ground. During slow charge, the voltage across the
current sense resistor is 15 mV with no connection to ADJ, and
it drops to 10 mV with a 100 k
resistor attached to ground.
Therefore, the maximum charge rate I
MAX
is calculated as
)(
)mV(
S
RS
MAX
R
V
I =
(1)
where 50 mV ≤ V
RS
≤ 150 mV.
After determining suitable values for V
RS
and R
S
, the value of
V
ADJ
and R
ADJ
are calculated as
V
mV
mVmV
7.66
50)( +
=
RS
ADJ
V
V
(2)
R
ADJ
= 100 kΩ ×
ADJ
ADJ
VV
V
3
(3)
Examples of resistor combinations are shown in Table 4.
Table 4. Examples of RS and R
ADJ
Selection
I
MAX
RS mΩ V
RS
mV V
ADJ
V R
ADJ
1.5 A 100 150 3 Open
1 A 100 100 2.25 300 K
750 mA 100 75 1.87 167 K
500 mA 100 50 1.5 100 K
750 mA 200 150 3 Open
500 mA 200 100 2.25 300 K
375 mA 200 75 1.87 167 K
250 mA 200 50 1.5 100 K
500 mA 300 150 3 Open
333 mA 300 100 2.25 300 K
250 mA 300 75 1.87 167 K
167 mA 300 50 1.5 100 K
SETTING THE MAXIMUM CHARGE TIME
The maximum charge time is intended as a safety mechanism
to prevent the charger from trickle charging the cell indefinitely.
It does not terminate charging under normal charging condi-
tions, but only when there is a failure to reach end-of-charge.
A typical cell charges at a 1 C rate in about 1.5 hours, depending
on the cell type, temperature, and manufacturer. Generally,
a three-hour time limit is sufficient to prevent a normal charge
cycle from being interrupted by the charge timer. It is recom-
mended that the cell manufacturer be consulted for timing
details.
The maximum charge time is set by selecting the value of the
CTIMER capacitor. Calculate the timer capacitance using
CTIMER = t
CHG
(minutes) ×
minutes1800
µF1
(4)
The precharge and end-of-charge periods are 1/6 the duration
of the fast charge time limit. The charge timers are completely
disabled by connecting the TIMER pin to ground. If the timers
are disabled, the FAULT and TIMEOUT states are never reached,
so the timers should only be disabled if charging is monitored
and controlled externally.
EXTERNAL CAPACITORS
Use an input supply capacitor (CIN) with a value in the
1 µF to 10 µF range and place it close to the ADP2291. This
should provide adequate input bypassing, but the selected
capacitor should be checked in the actual application circuit.
Check that the input voltage does not droop or overshoot
excessively during the start-up transient.
Use a battery output capacitor (COUT) with a value of at least
10 µF. This capacitance provides compensation when no battery
load is present. In addition, the battery and interconnections
appear inductive at high frequencies and must be accounted for
when the charger is operated with a battery load. Therefore, a
small amount of output capacitance is necessary to compensate
for the inductive nature of the battery and connections. Use a
minimum output capacitance value of 1 µF for applications
where the battery cannot be removed.
REVERSE INPUT PROTECTION
The Diode D1, shown in Figure 22 through Figure 25, is
optional. It is required only if the input adapter voltage can
be applied with a reverse polarity.
If the adapter voltage is high enough, a Schottky diode is recom-
mended to minimize the voltage difference from the adapter to
the charger input and the power dissipation. Choose a diode with
a continuous current rating high enough to handle battery charging
current at the maximum ambient temperature. Use a diode with a
voltage rating greater than the maximum adapter voltage.
ADP2291
Rev. A | Page 13 of 20
In cases where the voltage drop across the protection device
must be kept low, a P MOSFET is recommended. Connect the
MOSFET as shown in Figure 21.
ADP2291
RS
INPUT
4.6V–12V
IN
CHG
CIN
CS DRV
04873-021
Figure 21. Reverse Input Protection
EXTERNAL PASS TRANSISTOR
Choose the external PNP pass transistor based on the given
operating conditions and power handling capabilities. The pass
device is determined by the base drive available, the input and
output voltage, and the maximum charge current.
Select the pass transistor with a collector-emitter breakdown
voltage that exceeds the maximum adapter voltage. A V
CEO
rating of at least 15 V is recommended.
Providing a charge current of I
MAX
with a minimum base drive
of 40 mA requires a PNP beta of at least
β
MIN
=
mA40
MAXMAX I
I
I
=
Β
(5)
Note that the beta of a transistor drops off with collector
current. Therefore, make sure the beta at I
MAX
meets the
minimum requirement.
For cases where the adapter voltage is low (less than 5.5 V),
calculate the saturation voltage by
V
CE(SAT)
= V
ADAPTER(MIN)
V
PROTECT
V
RS
V
BAT
(6)
where V
PROTECT
is the forward drop of the reverse input
protection.
The power handling capability of the PNP pass transistor is
another important parameter. The maximum power dissipation
of the pass transistor is estimated using
P
DISS
(W) = I
MAX
× (V
ADAPTER(MAX)
− V
PROTECT
− V
RS
− V
BAT
) (7)
where V
RS
= 50 mV to 150 mV at V
ADJ
= 1.5 V to 3.0 V,
V
BAT
= 2.8 V, the lowest cell voltage where fast charge can occur.
Note that the adapter voltage can be either preregulated or
unregulated. In the preregulated case, the difference between
the maximum and minimum adapter voltage is small. In this
case, use the maximum regulated adapter voltage to determine
the maximum power dissipation. In the unregulated case, the
adapter voltage can have a wide range specified. However, the
maximum voltage specified is usually with no load applied.
Therefore, the worst-case power dissipation calculation often
leads to an over-specified pass device. In either case, it is best to
determine the load characteristics of the adapter to optimize the
charger design.
For example:
V
ADAPTER(MIN)
= 5.0 V
V
ADAPTER(MAX)
= 6.0 V
I
MAX
= 500 mA
V
PROTECT
= 0.2 V at 500 mA
V
ADJ
= 3 V
V
RS
= 150 mV
β
MIN
=
5.12
mA40
mA500
==
ΒI
I
MAX
V
CE(SAT)
= V
ADAPTER(MIN)
V
PROTECT
V
RS
V
BAT
= 5.0 V − 0.2 V − 0.15 V − 4.2 V
= 0.45 V
P
DISS
(W) = I
MAX
× (V
ADAPTER(MAX)
V
PROTECT
V
RS
V
BAT
)
= 0.50 A × (6.0 V − 0.2 V − 0.15 V − 2.8 V)
= 1.4 W
A guide for selecting the PNP pass transistor is shown in Table 5.
Table 5. PNP Pass Transistor Selection Guide
Vendor Part Number Package Max PD @ 25°C Beta @ 1 A VCE (SAT)
Fairchild
FSB6726
NZT45H8
SuperSOT
SOT223
0.5 W
1.5 W
150
110
0.5 V
0.1 V
ON Semiconductor®
MTB35200
BCP53T1
MMJT9435
TSOP-6
SOT223
SOT223
0.625 W
1.5 W
1.6 W
200
35
200
0.175 V
0.3 V
0.18 V
Philips BCP51 SOT223 1.3 W 50 0.5 V
ZETEX
ZXT10P20DE6
ZXT2M322
FZT549
FMMT549
SOT23-6
2 mm × 2 mm MLP
SOT223
SOT23
1.1 W
1.5 W
2 W
0.5 W
270
270
130
130
0.17 V
0.17 V
0.25 V
0.25 V
ADP2291
Rev. A | Page 14 of 20
TYPICAL APPLICATION CIRCUIT
A typical application circuit is shown in Figure 22. The circuit is
capable of a 750 mA charge current for an input voltage of 4.5 V
to 6 V. Higher input voltages can be used, but the increased power
dissipation of the pass device must be taken into account.
ADP2291
TIMER ADJ
RS
200m
Q1
FZT549
D1
BAT1000
CTIMER
100nF
INPUT
4
.6V–12V
+
IN
CHG
BAT
CIN
2.2µF
GND
CS DRV
COUT
10µF
04873-022
Figure 22. Typical Application Circuit
CHARGE TERMINATION
In some applications, the charger is required to terminate charg-
ing when the EOC threshold is reached. Automatic charger
restart is not desired. Adding components R1, C1, and Q2
terminates charging when the
CHG
pin opens and prevents
further charging until the adapter is removed and reasserted.
ADP2291
TIMER ADJ
RS
200m
Q1
FZT549
Q2
2N7002
D1
BAT1000
CTIMER
100nF
C1
100nF
INPUT
4.6V–12V
+
IN
CHG
BAT
CIN
2.2µF
R1
500k
GND
CS DRV
COUT
10µF
LI-ION
CELL
04873-023
Figure 23. Self-Termination Circuit
SELECTABLE CHARGE CURRENT
In applications where the charge current needs to be selectable,
use the circuit shown in Figure 24. This circuit allows a proces-
sor to determine if the charge current needs to be reduced due
to an input source limitation or a different battery capacity
option or simply to reduce the stress on the pass transistor.
R2 and Q2 allow the charge current to be selected between
high, which results in a charge current of 750 mA; and low,
which results in a charge current of 250 mA.
ADP2291
TIMER ADJ
RS
200m
R2
100k
Q1
FZT549
Q2
2N7002
D1
BAT1000
CTIMER
100nF
INPUT
4.6V–12V
+
IN
CHG
BAT
CIN
2.2µF
GND
CS DRV
LOW/HIGH
COUT
10µF
LI-ION
CELL
04873-024
Figure 24. Selectable Charge Current Circuit
THERMAL PROTECTION
In applications where the overall size must be small or the input
voltage range is wide, adding thermal regulation is suggested.
This allows the charger to monitor the temperature of the pass
device and decrease the charge current as the temperature
increases. By adding an NTC thermistor to the ADJ pin, it is
possible to accomplish this; however, care is still required to
ensure that the power dissipation of the pass device is not
exceeded.
ADP2291
TIMER ADJ
RS
200m
Q1
FZT549
R1
470k
NTC LOCATED
NEAR Q1
R2
100k
D1
BAT1000
CTIMER
100nF
INPUT
4.6V–12V
+
IN
CHG
BAT
CIN
2.2µF
GND
CS DRV
COUT
10µF
LI-ION
CELL
04873-025
Figure 25. Thermal Regulation Circuit
Some suggested NTC thermistor suppliers are listed in Table 6.
Table 6. NTC Thermistor Manufacturers
Vendor Part Number Website
BetaTHERM SMD2500KJ435J www.betatherm.com
Murata NCP18WM474J www.murata .com
Panasonic ERTJ0EV474J www.panasonic.com
Vishay 2322 615 1.474 www.vishay.com

ADP2291ARMZ-R7

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Compact 1.5A Linear Charger
Lifecycle:
New from this manufacturer.
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