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MC100EPT23MNR4

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 19
1 Publication Order Number:
MC100EPT23/D
MC100EPT23
3.3V Dual Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
Description
The MC100EPT23 is a dual differential LVPECL/LVDS/CML to
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only + 3.3 V and ground are required. The small
outline 8-lead SOIC package and the dual gate design of the EPT23
makes it ideal for applications which require the translation of a clock
or data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external V
BB
reference, the EPT23 does
not require both ECL standard versions. The LVPECL/LVDS inputs
are differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL/LVDS input referenced from a V
CC
of + 3.3 V.
Features
• 1.5 ns Typical Propagation Delay
• Maximum Operating Frequency > 275 MHz
• LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
• 24 mA LVTTL Outputs
• Operating Range:
♦ V
CC
= 3.0 V to 3.6 V with GND = 0 V
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M
= Date Code
G = Pb-Free Package
KA23
ALYWG
G
1
8
www.onsemi.com
KPT23
ALYW
G
1
8
3T M G
G
14
(Note: Microdot may be in either location)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
ORDERING INFORMATION
Device Package Shipping
†
MC100EPT23DG SOIC−8NB
(Pb-Free)
98 Units/Tube
MC100EPT23DR2G SOIC−8NB
(Pb-Free)
2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EPT23DTR2G 2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EPT23DTG 100 Units/Tube
DFN−8
(Pb-Free)
MC100EPT23MNR4G 1000/Tape & Reel
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAMS*
SOIC−8NB
D SUFFIX
CASE
751−07
TSSOP−8
DT SUFFIX
CASE
948R−02
1
8
1
8
DFN−8
MN SUFFIX
CASE 506AA
MC100EPT23
www.onsemi.com
2
1
2
3
45
6
7
8
Q0
GND
V
CC
Figure 1. Logic Diagram and 8-Lead Pinout
D0
Q1D1
D1
D0
LVPECL LVTTL
(Top View)
Table 1. PIN DESCRIPTION
Pin Function
Q0, Q1 LVTTL/LVCMOS Outputs
D0**, D1**
D0**, D1**
Differential LVPECL/LVDS/CML Inputs
V
CC
Positive Supply
GND Ground
EP (DFN−8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit.
Electrically connect to the most negative
supply (GND) or leave unconnected, floating
open.
** Pins will default to V
CC
/2 when left open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
50 kW
Internal Input Pullup Resistor
50 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−8NB
TSSOP−8
DFN−8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count 91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Power Supply GND = 0 V 3.8 V
V
I
Input Voltage GND = 0 V V
I
≤ V
CC
3.8 V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8NB 190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8 185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN−8 129
84
°C/W
MC100EPT23
www.onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol UnitRatingCondition 2Condition 1Parameter
T
sol
Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 1) DFN−8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
P1-P3P4-P6P7-P8

MC100EPT23MNR4

Mfr. #:
Buy MC100EPT23MNR4
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 3.3V Dual Diff
Lifecycle:
New from this manufacturer.
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