10
LTC3830/LTC3830-1
3830fa
The R
DS(ON)
of Q1 usually increases with temperature. To
keep the current limit threshold constant, the internal
12µA sink current at I
MAX
is designed with a positive
temperature coefficient to provide first order correction
for the temperature coefficient of R
DS(ON)Q1
.
In order for the current limit circuit to operate properly and
to obtain a reasonably accurate current limit threshold, the
I
IMAX
and I
FB
pins must be Kelvin sensed at Q1’s drain and
source pins. In addition, connect a 0.1µF decoupling
capacitor across R
IMAX
to filter switching noise. Other-
wise, noise spikes or ringing at Q1’s source can cause the
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
R
DS(ON)
, the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuit begins to take effect will vary from unit to unit as the
R
DS(ON)
of Q1 varies. Typically, R
DS(ON)
varies as much as
±40% and with ±25% variation on the LTC3830’s I
MAX
current, this can give a ±65% variation on the current limit
threshold.
The R
DS(ON)
is high if the V
GS
applied to the MOSFET is
low. This occurs during power up, when PV
CC1
is ramping
up. To prevent the high R
DS(ON)
from activating the current
limit, the LTC3830 disables the current limit circuit if
PV
CC1
is less than 2.5V above V
CC
. To ensure proper
operation of the current limit circuit, PV
CC1
must be at
least 2.5V above V
CC
when G1 is high. PV
CC1
can go low
when G1 is low, allowing the use of an external charge
pump to power PV
CC1
.
Oscillator Frequency
The LTC3830 includes an onboard current controlled
oscillator that typically free-runs at 200kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 200kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V, connecting
a 50k resistor from FREQSET to ground forces 25µA out
of the pin, causing the internal oscillator to run at approxi-
mately 450kHz. Forcing an external 10µA current into
FREQSET cuts the internal frequency to 100kHz. An inter-
nal clamp prevents the oscillator from running slower than
about 50kHz. Tying FREQSET to V
CC
forces the chip to run
at this minimum speed. The LTC3830-1 and the 8-lead
LTC3830 do not have this frequency adjustment function.
Shutdown
The LTC3830 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN for
more than 100µs forces the LTC3830 into shutdown
mode. In this mode, all internal switching stops, the COMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3830 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
V
IN
current to be some what higher, especially at elevated
temperatures. If SHDN returns high, the LTC3830 reruns
a soft-start cycle and resumes normal operation. The
LTC3830-1 does not have this shutdown function.
APPLICATIO S I FOR ATIO
WUUU
+
+
12
13
LTC3830
CC
12µA
0.1µF
Q2
C
OUT
3830 F04
C
IN
V
IN
V
OUT
G2
I
MAX
R
IMAX
I
FB
1k
+
Q1
L
O
G1
Figure 4. Current Limit Setting
11
LTC3830/LTC3830-1
3830fa
External Clock Synchronization
The LTC3830 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3830 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low, this forces the LTC3830 internal oscillator to
lock to the external clock frequency. The LTC3830-1 does
not have this external synchronization function.
The LTC3830 internal oscillator can be externally synchro-
nized from 100kHz to 500kHz. Frequencies above 300kHz
can cause a decrease in the maximum obtainable duty
cycle as rise/fall time and propagation delay take up a
larger percentage of the switch cycle. Circuits using these
frequencies should be checked carefully in applications
where operation near dropout is important—like 3.3V to
2.5V converters. The low period of this clock signal must
not be >100µs, or else the LTC3830 enters shutdown
mode.
Figure 5 describes the operation of the external synchro-
nization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that with the traditional sync method, the
ramp amplitude is lowered as the external clock frequency
goes higher. The effect of this decrease in ramp amplitude
increases the open-loop gain of the controller feedback
loop. As a result, the loop crossover frequency increases
and it may cause the feedback loop to be unstable if the
phase margin is insufficient.
To overcome this problem, the LTC3830 monitors the
peak voltage of the ramp signal and adjusts the oscillator
charging current to maintain a constant ramp peak.
APPLICATIO S I FOR ATIO
WUUU
SHDN
200kHz
FREE RUNNING
RAMP SIGNAL
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
TERMINATION
LTC3830
KEEPS RAMP
AMPLITUDE
CONSTANT
UNDER SYNC
RAMP SIGNAL
WITH EXT SYNC
RAMP AMPLITUDE
ADJUSTED
3830 F05
Figure 5. External Synchronization Operation
3830 F6
+
V
CC
PV
CC2
PV
CC1
V
IN
G1
Q1
C
OUT
V
OUT
Q2
L
O
G2
INTERNAL
CIRCUITRY
LTC3830 (16-LEAD)
3830 F7
+
V
CC
/PV
CC2
PV
CC1
V
IN
G1
Q1
C
OUT
V
OUT
Q2
L
O
G2
INTERNAL
CIRCUITRY
LTC3830 (8-LEAD)
Figure 6. 16-Lead Power Supplies
Figure 7. 8-Lead Power Supplies
12
LTC3830/LTC3830-1
3830fa
Input Supply Considerations/Charge Pump
The 16-lead LTC3830 requires four supply voltages to
operate: V
IN
for the main power input, PV
CC1
and PV
CC2
for
MOSFET gate drive and a clean, low ripple V
CC
for the
LTC3830 internal circuitry (Figure 6). The LTC3830-1 and
the 8-lead LTC3830 have the PV
CC2
and V
CC
pins tied
together inside the package (Figure 7). This pin, brought
out as V
CC
/PV
CC2
, has the same low ripple requirements
as the 16-lead part, but must also be able to supply the gate
drive current to Q2.
In many applications, V
CC
can be powered from V
IN
through an RC filter. This supply can be as low as 3V. The
low quiescent current (typically 800µA) allows the use of
relatively large filter resistors and correspondingly small
filter capacitors. 100 and 4.7µF usually provide ad-
equate filtering for V
CC
. For best performance, connect the
4.7µF bypass capacitor as close to the LTC3830 V
CC
pin as
possible.
Gate drive for the top N-channel MOSFET Q1 is supplied
from PV
CC1
. This supply must be above V
IN
(the main
power supply input) by at least one power MOSFET V
GS(ON)
for efficient operation. An internal level shifter allows PV
CC1
to operate at voltages above V
CC
and V
IN
, up to 14V maxi-
mum. This higher voltage can be supplied with a separate
supply, or it can be generated using a charge pump.
Gate drive for the bottom MOSFET Q2 is provided through
PV
CC2
for the 16-lead LTC3830 or V
CC
/PV
CC2
for the
LTC3830-1 and the 8-lead LTC3830. This supply only
needs to be above the power MOSFET V
GS(ON)
for efficient
operation. PV
CC2
can also be driven from the same supply/
charge pump for the PV
CC1
, or it can be connected to a
lower supply to improve efficiency.
Figure 8 shows a tripling charge pump circuit that can be
used to provide 2V
IN
and 3V
IN
gate drive for the external
top and bottom MOSFETs respectively. These should fully
enhance MOSFETs with 5V logic level thresholds. This
circuit provides 3V
IN
– 3V
F
to PV
CC1
while Q1 is ON and
2V
IN
– 2V
F
to PV
CC2
where V
F
is the forward voltage of the
Schottky diodes. The circuit requires the use of Schottky
diodes to minimize forward drop across the diodes at
start-up. The tripling charge pump circuit can rectify any
ringing at the drain of Q2 and provide more than 3V
IN
at
PV
CC1
; a 12V zener diode should be included from PV
CC1
to PGND to prevent transients from damaging the circuitry
at PV
CC1
or the gate of Q1.
The charge pump capacitors refresh when the G2 pin goes
high and the switch node is pulled low by Q2. The G2 on-
time becomes narrow when LTC3830 operates at maxi-
mum duty cycle (95% typical), which can occur if the input
supply rises more slowly than the soft-start capacitor or
the input voltage droops during load transients. If the G2
on-time gets so narrow that the switch node fails to pull
completely to ground, the charge pump voltage may
collapse or fail to start, causing excessive dissipation in
external MOSFET Q1. This is most likely with low V
CC
voltages and high switching frequencies, coupled with
large external MOSFETs which slow the G2 and switch
node slew rates.
APPLICATIO S I FOR ATIO
WUUU
Figure 8. Tripling Charge Pump
LTC3830
3830 F08
+
D
Z
12V
1N5242
10µF
G1
G2
0.1µF
Q1
L
O
Q2 C
OUT
V
OUT
0.1µF
PV
CC2
1N5817
1N5817
1N5817
PV
CC1
V
IN

LTC3830-1ES8#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr Buck Sync DC/DC Cntrs for L V Ope
Lifecycle:
New from this manufacturer.
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