AD694JNZ Datasheet AD694JNZ, AD694ARZ-REEL, AD694BRZ | P7-P9

AD694

–6–

REV. B

An NPN boost transistor can be added in the 2 V mode to in-

crease the current drive capability of the 2 V reference. The

10 V force pin is connected to the base of the NPN, and the

NPN emitter is connected to the 2 V sense pin. The minimum

Of the part increases by approximately 0.7 V.

4.5 V SINGLE SUPPLY OPERATION

For operation with a 4.5 V power supply, the input span and the

voltage reference output must be reduced to give the amplifiers

their required 2.5 V of headroom for operation. This is done by

adjusting the AD694 for 2 V full-scale input, and a voltage ref-

erence output of 2 V as described above.

GENERAL DESIGN GUIDELINES

A 0.1 µF decoupling capacitor is recommended in all applica-

tions from V

(Pin 13) to Com (Pin 5). Additional components

may be required if the output load is nonresistive, see section on

driving nonresistive loads. The buffer amplifier PNP inputs

should not be brought more negative than –0.3 V from com-

mon, or they will begin to source large amounts of current. In-

put protection resistors must be added to the inputs if there is a

danger of this occurring. The output of the buffer amplifier, Pin

1 (FB), is not short circuit protected. Shorting this pin to

ground or V

with a signal present on the amplifier may damage

it. Input signals should not drive Pin 1 (FB) directly; always use

the buffer amplifier to buffer input signals.

DRIVING NONRESISTIVE LOADS

The AD694 is designed to be stable when driving resistive loads.

Adding a 0.01 µF capacitor from I

OUT

(Pin 11) to Com (Pin 5),

as shown in Figure 3, ensures the stability of the AD694 when

driving inductive or poorly defined loads. This capacitor is rec-

ommended when there is any uncertainty as to the characteris-

tics of the load.

Figure 3. Capacitor Utilized When Driving Nonresistive

Loads; Protection Diodes Used When Driving Inductive

Loads

Additional protection is recommended when driving inductive

loads. Figure 3 shows two protective diodes, D1 and D2, added

to protect against voltage spikes that may extend above V

below common that could damage the AD694. These diodes

should be used in addition to the 0.01 µF capacitor. When the

optional NPN transistor is used, the capacitor and diodes

should connect to the NPN emitter instead of Pin 11.

0-20 mA OPERATION

A 0–20 mA output range is available with the AD694 by remov-

ing the 4 mA offset current with the 4 mA On/Off pin. In nor-

mal 4–20 mA operation, the 4 mA On/Off (Pin 9) is tied to

ground, enabling the 4 mA offset current. Tying Pin 9 to a po-

tential of 3 V or greater turns off the 4 mA offset current; con-

necting Pin 9 to the 10 V reference, the positive supply, or a

TTL control pin, is a convenient way to do this. In 0–20 mA

mode, the input span is increased by 20%, thus the

precalibrated input spans of 2 V and 10 V become 2.5 V and

12.5 V. Minimum supply voltages for the two spans increase to

5 V and 15 V.

The 4 mA On/Off pin may also be used as a “jiggle pin” to

unstick valves or actuators, or as a way to shut off a 4–20 mA

loop entirely. Note that the pin only removes the 4 mA offset

and not the signal current.

DUAL SUPPLY OPERATION

Figure 4 shows the AD694 operated in dual supply mode. (Note

that the pass transistor is shown for illustration and is not re-

quired for dual supply operation.) The device is powered com-

pletely by the positive supply which may be as low as 4.5 V. The

unique design of the output stage allows the I

OUT

pin to extend

below common to a negative supply. The output stage can

source a current to a point 36 V below the positive supply. For

example, when operated with a 12.5 V supply, the AD694 can

source a current to a point as low as 23.5 V below common.

This feature can simplify the interface to dual supply DACs by

eliminating grounding and level-shifting problems while increas-

ing the load that the transmitter is able to drive. Note that the

OUT

pin is the only pin that should be allowed to extend lower

than –0.3 V of common.

OPERATION WITH A PASS TRANSISTOR

The AD694 can operate as a stand-alone 4–20 mA converter

with no additional active components. However, provisions have

been made to connect I

OUT

to the base of an external NPN pass

transistor as shown in Figure 4. This permits a majority of the

power dissipation to be moved off-chip to enhance performance

and extend the temperature range of operation. Note that the

positive output voltage compliance is reduced by approximately

0.7 V, the V

of the pass device. A 50 Ω resistor should be

added in series with the pass transistor collector, when the

AD694 is operated with dual supplies, as shown in Figure 4.

This will not reduce the voltage compliance of the output stage.

The external pass transistor selected should have a BV

CEO

greater than the intended supply voltage with a sufficient power

rating for continuous operation with 25 mA current at the sup-

ply voltage. F

should be in the 10 MHz to 100 MHz range and

β should be greater than 10 at a 20 mA emitter current. Heat

sinking the external pass transistor is suggested.

AD694

REV. B

–7–

Figure 4. Using Optional Pass Transistor to Minimize Self-Heating Errors; Dual Supply Operation Shown

POWER DISSIPATION CONSIDERATIONS

The AD694 is rated for operation over its specified temperature

without the use of an external pass transistor. However, it is

possible to exceed the absolute maximum power dissipation,

with some combinations of power supply voltage and voltage

reference load. The internal dissipation of the part can be calcu-

lated to determine if there is a chance that the absolute maxi-

mum dissipation may be exceeded. The die temperature must

never exceed 150°C.

Total power dissipation (P

TOT

), is the sum of power dissipated

by the internal amplifiers, P (Standing), the voltage reference,

P(V

REF

) and the current output stage, P(I

OUT

) as follows:

TOT

= P (Standing) + P (V

REF

) + P (I

OUT

)

where:

P (Standing) = 2 mA (max) × V

P (V

REF

) = (V

– V

REF

) × I

VREF

P(I

OUT

) (V

– V

OUT

) × I

OUT

(max):

OUT

(max) may be the max expected operating cur-

rent, or the overdriven current of the device.

P(I

OUT

) drops to (2 V × I

OUT

) if a pass transistor

is used.

Definitions:

REF

= output voltage of reference

VREF

= output current of reference

= supply voltage

OUT

= voltage at I

OUT

pin.

An appropriate safety factor should be added to P

TOT

The junction temperature may be calculated with the following

formula:

= P

TOT

(

) + T

AMBIENT

is the thermal resistance between the chip and the package

(case), θ

is the thermal resistance between the case and its

surroundings and is determined by the characteristics of the

thermal connection of the case to ambient.

For example, assume that the part is operating with a V

of 24 V

in the CERDIP package at 50°C, with a 1 mA load on the 10 V

reference. Assume that I

OUT

is grounded and that the max I

OUT

would be 20 mA. The internal dissipation would be:

TOT

) = 2 mA

24 V + (24 V – 10 V)

1 mA + (24 V – 0 V)

20 mA

= 48 mW + 14 mW + 480 mW = 542 mW

Using θ

of 30°C/W and θ

of 70°C/W (from specifications

page), the junction temperature is:

= 542 mW (30

C/W + 70

C/W) + 50

C = 104.2

The junction temperature is in the safe region.

Internal power dissipation can be reduced either by reducing the

value of θ

through the use of air flow or heat sinks, or by re-

ducing P

TOT

of the AD694 through the use of an external pass

transistor. Figure 5 shows the maximum case and still air tem-

peratures for a given level of power dissipation.

Figure 5. Internal Power Dissipation in mW

ADJUSTMENT PROCEDURES

The following sections describe methods for trimming the out-

put current offset, the span, and the voltage reference.

ADJUSTING 4 mA ZERO

The 4 mA zero current may be adjusted over the range of 2 mA

to 4.8 mA to accommodate large input signal offsets, or to allow

small adjustment in the zero current. The zero may be adjusted

by pulling up or down on Pin 6 (4 mA Adj) to increase or de-

crease the nominal offset current. The 4 mA Adj. (Pin 6) should

not be driven to a voltage greater than 1 V. The arrangement of

AD694

–8–

REV. B

Figure 6 will give an approximately linear adjustment of the

4 mA offset within fixed limits. To find the proper resistor val-

ues, first select X, the desired range of adjustment as a fraction

of 4 mA. Substitute this value in the appropriate formula below

along with the chosen reference output voltage (V

REF

= 2 V or

10 V usually), to determine the resistor values required.

= 180

Ω

(1/X – 4.5)

= 500

Ω

[(V

REF

/ 1.22 V) – 0.18 – 0.82X][1/X – 4.5]

These formulae take into account the ± 10% internal resistor

tolerance and ensure a minimum adjustment range for the 4 mA

offset. For example, assume the 2 V reference option has been

selected. Choosing X = 0.05, gives an adjustment range of ±5%

of the 4 mA offset.

= 180

Ω

(1/0.05 – 4.5) = 2.79 k

Ω

= 500

Ω

[(2 V / 1.22) – 0.18 – 0.82

0.05][1/0.05 – 4.5]

= 10.99 k

Ω

These can be rounded down to more convenient values of

2.5 kΩ and 9.76 kΩ. In general, if the value of R

is rounded

down slightly, the value of R

should be rounded down propor-

tionately, and vice versa. This helps to keep the adjustment

range symmetrical.

Figure 6. Optional 4 mA Zero Adjustment

ADJUSTING SPAN FOR 10 V FS

When the AD694 is configured with a 10 V input full-scale the

span maybe adjusted using the network shown in Figure 7. This

scheme allows an approximately linear adjustment of the span

above or below the nominal value. The span adjustment does

not interact with the 4 mA offset. To select R

and R

, choose

Figure 7. Span Adjustment, 10 V Full Scale

X, the desired adjustment range as a fraction of the span. Sub-

stitute this value in the appropriate formula below.

= 1.8 k

Ω

((1 – X)/X)

= 9 k

Ω

[1 – 0.2 (1 + X)( 1 – X )] / 2X

These formulae take into account the ± 10% absolute resistor

tolerance of the internal span resistors and ensure a minimum

adjustment range of the span. For example, choosing the adjust-

ment range to be ±2%, or 0.02 gives:

= 1.8 k

Ω

((1 – 0.02) / 0.02) = 88.2 k

Ω

= 9 k

Ω

[1 – 0.2 (1 + 0.02)( 1 – 0.02 )] / (2

0.02) =

175.5 k

Ω

These values can be rounded up to the more convenient values

of 100 kΩ and 198 kΩ. In general, if R

is rounded up, then the

value of R

should be rounded up proportionally, and vice versa.

ADJUSTING SPAN FOR 2 V FS

The precalibrated 2 V full-scale range requires a different ad-

justment scheme due to the single supply nature of the AD694.

Figure 8 shows an adjustment scheme that allows an approxi-

mately linear adjustment of the 2 V span plus or minus the

nominal value. The span adjustment does not affect the value of

the 4 mA offset current.

To find the proper resistor values first select X, the desired

range of adjustment as a fraction of the output span. Substitute

this value into the following formulae:

= 2 × X × R

where R

is greater than 5 K

= (2.75 kΩ × X)/(1 – 0.275X)

These formulae take into account the ± 10% absolute tolerance

of the internal span resistors and ensure a minimum adjustment

range.

For example, choosing the adjustment range to be ± 320 µA of

FS or, ±2%, let X = 0.02. Thus:

Setting R

= 10 K, then R

= 2(.02)

10 kΩ = 400 Ω

= (2.75 kΩ

0.02)/ (1 – 0.275

(0.02)) = 55.3 Ω

The value of R

can be rounded to the more convenient value of

49.9 Ω. In general, if R

is rounded up, then R

should be

rounded up proportionally, and vice versa; rounding up will in-

crease the range of adjustment.

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Instrumentation Amplifiers IC 4-20mA Mono Current Transmitter

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