©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD0708, FOD0738 Rev. 1.0.8 3
FOD0708 Single Channel CMOS Optocoupler, FOD0738 Dual Channel CMOS Optocoupler
Switching Characteristics
Over recommended temperature (T
A
= –40°C to +100°C) and
4.5 V
≤
V
DD
≤
5.5 V. All typical specifications are at T
A
= 25°C, V
DD
= +5 V.
*All typicals at T
A
= 25°C and V
DD
= 5V unless otherwise noted.
Isolation Characteristics
(T
A
= -40°C to +100°C Unless otherwise specified.)
*All typical values are at V
CC
= 5 V, T
A
= 25°C
Notes:
1. Propagation delay time, high to low (t
PHL
), is measured from the 50% level on the rising edge of the input pulse to
the 2.5V level of the falling edge of the output voltage signal. Propagation delay time, low to high (t
PLH
), is measured
from the 50% level on the falling edge of the input pulse to the 2.5V level of the rising edge of the output voltage
signal.
2. Pulse width distoration is defined as the absolute difference between the high to low and low to high propagation
delay times, | t
PHL
– t
PLH
|.
3. Propagation delay skew, t
PSK
, is defined as the worst case difference in t
PHL
or t
PLH
between units within the
recommended operating range of the device.
4. CM
H
– The maximum tolerated rate of rise of the common mode voltage to ensure the output will remain in the high
state, (i,e., V
OUT
> 2.0V) Measured in kilovolts per microsecond (kV/µs).
5. CM
L
– The maximum tolerated rate of fall of the common mode voltage to ensure the output will remain in the low
state, (i,e., V
OUT
< 0.8V). Measured in kilovolts per microsecond (kV/µs).
6. Isolation voltage, V
ISO
, is an internal device dielectric breakdown rating. For this test, pins 1,2,3,4 are common, and
pins 5,6,7,8 are common.
Symbol Parameter Test Conditions Min. Typ.* Max. Units
t
PHL
Propagation Delay Time to
Logic Low Output
I
F
= 12mA, C
L
= 15pF
CMOS Signal Levels (Note 1) (Fig. 10)
20 60 ns
t
PLH
Propagation Delay Time to
Logic High Output
I
F
= 12mA, C
L
= 15pF
CMOS Signal Levels,
(Note 1) (Fig. 10)
FOD0708
13 60 ns
FOD0738
11 60
PW Pulse Width 100 ns
| PWD | Pulse Width Distortion I
F
= 12mA, C
L
= 15pF,
CMOS Signal Levels (Note 2)
0 30 ns
t
PSK
Propagation Delay Skew I
F
= 12mA, C
L
= 15pF,
CMOS Signal Levels (Note 3)
40 ns
t
R
Output Rise Time (10%–90%) I
F
= 12mA, C
L
= 15pF,
CMOS Signal Levels
12 ns
t
F
Output Fall Time (90%–10%) I
F
= 12mA, C
L
= 15pF,
CMOS Signal Levels
8 ns
| CM
H
| Common Mode Transient
Immunity at Logic High
Output
V
CM
= 1000V, T
A
= 25°C, I
F
= 0mA,
(Note 4) (Fig. 11)
25 50 kV/µs
| CM
L
| Common Mode Transient
Immunity at Logic Low Output
V
CM
= 1000V, T
A
= 25°C, I
F
= 12mA,
(Note 5) (Fig. 11)
25 50 kV/µs
Characteristics Test Conditions Symbol Min Typ.* Max Unit
Input-Output Insulation
Leakage Current
Relative humidity = 45%,
T
A
= 25°C, t = 5s,
V
I-O
= 3000 VDC (Note 6)
I
I-O
1.0 µA
Withstand Insulation
Test Voltage
I
I-O
≤
10µA, R
H
< 50%,
T
A
= 25°C, t = 1 min. (Note 6)
V
ISO
2500 V
RMS
Resistance (Input to Output) V
I-O
= 500V (Note 6) R
I-O
10
12
Ω
Capacitance (Input to Output) f = 1MHz (Note 6) C
I-O
0.6 pF
