87158AG www.idt.com REV. C JULY 25, 2010
10
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS
÷1, ÷2, ÷4 CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows an example of the ICS87158 LVPECL to
HCSL Clock Generator schematic.
In this example, the ICS87158 is configured as follows:
PWR_DWN# = 1
Mult_[1:0] = 10, Rref = 475Ω, IREF = 2.32mA, I
OH
= 6*IREF
SEL_[A,B,U] = 000, MREF = PECL ÷ 4, all HOST output = PECL ÷ 2
SEL_T = 0, Output Enable
Zo = 50
50MHz,
LVCMOS/LVTTL
C10
0.1uF
C10
0.1uF
Zo = 50
Zo = 50
200MHz, 3.3V
LVPECL
ICS8431-11
(U1-13)
R2
50
3.3V LVPECL
R8
28
+
-
R4
50
(U1-19)
R9
28
Zo = 50
(U1-28) (U1-40)
Zo = 50
(U1-14)
VDD=3.3V
(U1-23)
R5
50
C10
0.1uF
ICS9222-01_REFCLK
(U1-34)
C5
0.1uF
(U1-48)
ICS9222-01_REFCLK
C6
0.1uF
ICS8431-01
U1
85158
1
2
3
4
5
6
7
8
9
10
35
36
25
27
28
32
31
29
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
30
33
34
42
41
40
39
38
37
46
45
44
43
47
48
GND
VDD
VDD_R
PECL
nPECL
GND_R
VDD_M
MREF
nMREF
GND_M
HOST_N4
HOST_P4
VDD_I
IREF
VDD_H
HOST_N5
GND_H
HOST_N6
VDD
GND
VDD_L
VDD
GND_L
SEL_T
MULT_0
MULT_1
VDD_L
GND_L
SEL_A
SEL_B
SEL_U
PWR_DWN#
GND_I
HOST_P6
HOST_P5
VDD_H
HOST_P2
HOST_N2
VDD_H
HOST_P3
HOST_N3
GND_H
VDD_H
HOST_P1
HOST_N1
GND_H
GND_H
VDD
C9
0.1uF
VDD=3.3V
C4
0.1uF
Zo = 50
100MHz,
HCSL
Rref
475
C3
0.1uF
C7
0.1uF
(U1-46)
C8
0.1uF
(U1-11)
C10
0.1uF
(U1-2) (U1-25)(U1-7)
C5
0.1uF
R6
33
C9
0.1uF
R1
50
VDD=3.3V
R7
33
R3
50
FIGURE 3. ICS87158 SCHEMATIC LAYOUT
87158AG www.idt.com REV. C JULY 25, 2010
11
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS
÷1, ÷2, ÷4 CLOCK GENERATOR
Power and Ground
This section provides a layout guide related to power,
ground and placement of bypass capacitors for a high-
speed digital IC. This layout guide is a general recommen-
dation. The actual board design will depend on the compo-
nent types being used, the board density and cost con-
straints. The description assumes that the board has clean
power and ground planes. The principle is to minimize the
ESR between the clean power/ground plane and the IC
power/ground pin.
A low ESR bypass capacitor should be used on each power
pin. The value of bypass capacitors ranges from 0.01uF to
0.1uF. The bypass capacitors should be located as close
IC
C
VIA
GND Pin
Power
Pin
GND
Pads
POWER
Pads
FIGURE 4. RECOMMENDED LAYOUT OF BYPASS CAPACITOR PLACEMENT
to the power pin as possible. It is preferable to locate the
bypass capacitor on the same side as the IC. Figure 4
shows suggested capacitor placement. Placing the by-
pass capacitor on the same side as IC allows the capaci-
tor to have direct contact with the IC power pin. This can
avoid any vias between the bypass capacitor and the IC
power pins.
The vias should be place at the Power/Ground pads. There
should be minimum one via per pin. Increase the number
of vias from the Power/Ground pads to Power/Ground
planes can improve the conductivity.
87158AG www.idt.com REV. C JULY 25, 2010
12
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS
÷1, ÷2, ÷4 CLOCK GENERATOR
D2
B) Input with internal pull down resistor
D2
INPUT_DOWN
D1D1
INPUT_PU
RU
51K
VDD
RD
51K
VDD
A) Input with internal pull up resistor
LOGIC CONTROL INPUT
The logic input control signals are 3.3V LVCMOS compatible.
The logic control input contains ESD diodes and either pull-up
or pull-down resistor as shown in Figure 5. The data sheet pro-
vides pull-up or pull-down information for each input pin. Leav-
ing the input floating will set the control logic to default setting.
HCSL DRIVER TERMINATION
The HCSL is a differential constant current source driver. The
output current is set by control pins MULT_[1:0] and the value of
resistor Rref.
In the characteristic impedance of 50 Ohm environment, the
match load 50 Ohm resistors R4 and R5 are terminated at the
receiving end of the transmission line. The 33 Ohm series resis-
tor R6 and R7 should be located as close to the driver pins as
possible. For the clock traces that required very low skew should
have equal length.
Other general rules of high-speed digital design also should be
followed. Some check points are listed as follows:
- Avoid sharp angles on the clock trace. Sharp angle turn
causes the characteristic impedance change on the
transmission lines.
- Keep the clock trace on same layer. Whenever possible,
avoid any vias on the middle clock traces. Any via on
middle the trace can affect the trace characteristic
impedance and hence degrade signal quality.
- There should be sufficient space between the clock traces
that have different frequencies to avoid cross talk.
- No other signal trace is routed between the clock trace
pair.
- Transmission line should not be routed across the split
plane on the adjacent layer.
To set logic high, the input pin connected directly to V
DD
. To set
logic low, the control input connect directly to ground. For con-
trol signal source from the driver that has different power sup-
ply, a series current resistor of greater than 100 Ohm is required
for random power on sequence.
FIGURE 5. LOGIC INPUT CONTROLS

87158AFLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 6 HCSL 2 CMOS OUT BUFFER/DIV
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet