1. General description
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting
registered transceiver. Two 8-bit back to back registers store data flowing in both
directions between two bidirectional buses. Data applied to the inputs is entered and
stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable
(nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only
accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A
inputs to B outputs is the same as for B inputs to A outputs.
2. Features
n CMOS low-power consumption
n Multibyte flow-through pinout architecture
n Low inductance, multiple center power and ground pins for minimum noise and ground
bounce
n Direct interface with TTL levels
n Output drive capability 50 Ω transmission lines at 85 °C
n Complies with JEDEC standard JESD8-B
3. Quick reference data
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
= C
PD
× V
CC
2
× f
i
× N + Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
Σ(C
L
× V
CC
2
× f
o
) = sum of outputs.
74ALVCH16952
16-bit registered transceiver; 3-state
Rev. 02 — 27 April 2006 Product data sheet
Table 1. Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns.
Symbol Parameter Conditions Min Typ Max Unit
t
PHL
,
t
PLH
propagation delay
nCPBA to nAn; nCPAB to nBn V
CC
= 3.3 V; C
L
= 50 pF - 3.2 - ns
V
CC
= 2.5 V; C
L
= 30 pF - 3.2 - ns
f
max
maximum input clock
frequency
V
CC
= 3.3 V - 350 - MHz
C
i
input capacitance - 3.0 - pF
C
PD
power dissipation capacitance per buffer; V
I
= GND to V
CC
[1]
-30-pF
