6.42
IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range
13
R/
W
ADDRESS
An An +1 An + 2 An + 2
An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
5682 drw 11
Qn
Qn + 3
DATA
OUT
CE
1
BE
n
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ NOP READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
,
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)
(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An An +1 An + 2 An + 3
An + 4
An + 5
DATA
IN
Dn + 3Dn + 2
CE
0
CLK
5682 drw 12
DATA
OUT
Qn
Qn + 4
CE
1
BE
n
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ WRITE READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
,
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
