4
Troubleshooting
► The FFT plot appears abnormal...
If you see a normal noise floor when you disconnect the signal generator from the
analog input, be sure you are not overdriving the ADC. Reduce input level if
necessary.
In VisualAnalog, Click on the Settings button in the “Input Formatter” block. Check
that “Number Format” is set to the correct encoding (2’s compliment by default).
► The FFT plot appears normal, but performance is poor.
Make sure you are using an appropriate filter on the analog input.
Make sure the signal generators for the clock and the analog input are clean (low
phase noise).
If you are using non-coherent sampling, change the analog input frequency slightly.
Make sure the SPI config file matches the product being evaluated.
► The FFT window remains blank after the Run button is clicked.
Make sure the evaluation board is securely connected to the HSC-ADC-EVALCZ
board
Repeat steps 8 through 12.
Make sure the FPGA has been programmed by verifying that the ‘D6’ LED is
illuminated on the HSC-ADC-EVALCZ board.
Make sure the correct FPGA program was installed.
► VisualAnalog indicates that the “FIFO capture timed out.”
Make sure all power and USB connections are secure.
Repeat steps 11 through 14.
Double check that the encode clock source is present at connector J506.
Revision: 3 November 4, 2011
