DS2756: High-Accuracy Battery Fuel Gauge with Programmable Suspend Mode
EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data
command is in progress. While this
bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data can be written to unlocked
EEPROM blocks.
LOCK—EEPROM Lock Enable. When this bit is 0, the Lock command is ignored. Writing a 1 to this bit enables the
Lock command. After the Lock command is executed, the LOCK bit is reset to 0. The factory default is 0.
BL2—EEPROM Block 2 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 2 (addresses 60h to 7Fh)
is locked (read-only), while a 0 indicates block 1 is unlocked (read/write).
BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 40h to 5Fh)
is locked (read-only), while a 0 indicates block 1 is unlocked (read/write).
BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20h to 3Fh)
is locked (read-only), while a 0 indicates block 0 is unlocked (read/write).
X—Reserved Bits.
SPECIAL FEATURE REGISTER
The format of the Special Feature Register is shown in Figure 17. The function of each bit is described in detail in
the following paragraphs.
Figure 17. Special Feature Register Format
Address 08h
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
POR PIO X X X IE X SNAP
POR—POR Indicator bit. This bit is set to a 1 when the DS2756 experiences a power-on-reset (POR) event. To
use the POR bit to detect a power-on-reset, the POR bit must be set to a 0 by the host system upon power-up and
after each subsequent occurrence of a POR. This bit is read/write to 0.
PIO—PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.
IE—Interrupt Enable. A value of 1 in this bit location enables Alarm Comparator interrupt signaling to the host
system. When IE is 0, Alarm Comparator interrupt signaling is disabled and the alarm comparator registers are
available as SRAM and have no effect on device operation. IE bit is read/write to 1. IE is cleared to 0 by a 1-Wire
RESET on DQ.
SNAP—Snapshot Control. This bit is set to a 1 immediately after the DS2756 executes a Snapshot conversion
pair. SNAP = 1 indicates that the Current and Voltage registers contain Snapshot results. While SNAP = 1, the
Snapshot results persist in the Current and Voltage registers until the SNAP bit is written to a 0 by the host system.
This bit is read/write to 0.
X—Reserved Bits.
19 of 27
DS2756: High-Accuracy Battery Fuel Gauge with Programmable Suspend Mode
1-Wire BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-Wire bus
with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2756 is a slave device.
The bus master is typically a microprocessor in the host system. The discussion of this bus system consists of four
topics: 64-Bit Net Address, Hardware Configuration, Transaction Sequence, and 1-Wire Signaling.
64-BIT NET ADDRESS
Each DS2756 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first 8 bits are the
1-Wire family code (35h for DS2756). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the
first 56 bits (see Figure 18). The 64-bit net address and the 1-Wire I/O circuitry built into the device enable the
DS2756 to communicate through the 1-Wire protocol detailed in the 1-Wire Bus System section of this data sheet.
Figure 18. 1-Wire Net Address Format
8-Bit CRC 48-Bit Serial Number
8-Bit Family
Code (35h)
MSb LSb
CRC GENERATION
The DS2756 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure error-free
transmission of the address, the host system can compute a CRC value from the first 56 bits of the address and
compare it to the CRC from the DS2756. The host system is responsible for verifying the CRC value and taking
action as a result. The DS2756 does not compare CRC values and does not prevent a command sequence from
proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a
very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a Shift Register and XOR gates as shown in
Figure 19, or it can be generated in software. Additional information about the Dallas 1-Wire CRC is available in
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor i
Button
Products.
Figure 19. 1-Wire CRC Generation Block Diagram
20 of 27
In the circuit in Figure 19, the shift bits are initialized to 0. Then, starting with the least significant bit of the family
code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is
entered. After the 48th bit of the serial number has been entered, the Shift Register contains the CRC value.
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the
appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain
or tri-state output drivers. The DS2756 uses an open-drain output driver as part of the bidirectional interface
circuitry shown in Figure 20. If a bidirectional pin is not available on the bus master, separate output, and input pins
can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the value of
this resistor should be approximately 5k. The idle state for the 1-Wire bus is high. If, for any reason, a bus
transaction must be suspended, the bus must be left in the idle state in order to properly resume the transaction
MSb
XOR
XOR
LSb
XOR
INPUT
iButton is a registered trademark of Dallas Semiconductor.
DS2756: High-Accuracy Battery Fuel Gauge with Programmable Suspend Mode
later. If the bus is left low for more than
120s, slave devices on the bus begin to interpret the low period as a reset
pulse, effectively terminating the transaction.
Figure 20. Typical 1-Wire Bus Interface Circuitry
1
A
Typ.
100
MOSFET
Tx
Rx
Rx
Tx
Rx =
Receive
Tx = TRANSMIT
V
PULLUP
(2.0V to 5.5V)
4.7k
BUS MASTER DS275x 1-WIRE PORT
The pullup must be disabled to allow the DS2756 to enter Suspend mode. The internal pulldown on the DS2756
DQ input ensures that DQ will be pulled to a logic low when the pullup is simply disconnected. With a
microcontroller, the pullup resistor can be connected between a general purpose port pin and the DS2756 DQ
terminal as shown in Figure 1. The GPIO pin, labeled Pullup Control, can be driven high for Active mode. The pin
labeled Data I/O is used bidirectionally for serial communication. When Standby mode is desired, the Pullup
Control pin can be driven low or floated in the high-Z state. If the current reading falls within the range of the
suspend thresholds, the DS2756 will enter Suspend if configured to do so (PMOD = 1 and PIE 00).
TRANSACTION SEQUENCE
The protocol for accessing the DS2756 through the 1-Wire port is as follows:
Initialization
Net Address Command
Function Command
Transaction/Data
The sections that follow describe each of these steps in detail.
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the
bus master followed by a presence pulse simultaneously transmitted by the DS2756 and any other slaves on the
bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For
more details, see the I/O Signaling section.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each command is followed by the 8-bit opcode for
that command in square brackets. Figure 21 presents a transaction flowchart of the net address commands.
Read Net Address [33h or 39h]. This command allows the bus master to read the DS2756’s 1-Wire net address.
This command can only be used if there is a single slave on the bus. If more than one slave is present, a data
collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The
RNAOP bit in the Status Register selects the opcode for this command, with RNAOP = 0 indicating 33h and
RNAOP = 1 indicating 39h.
Match Net Address [55h]. This command allows the bus master to specifically address one DS2756 on the 1-Wire
bus. Only the addressed DS2756 responds to any subsequent function command. All other slave devices ignore
21 of 27

DS2756E+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Battery Management High-Accuracy Bat Fuel Gauge
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet