844003AKI-04LFT Datasheet 844003AKI-04LF, 844003AKI-04LFT | P10-P12

844003I-04 Datasheet

Parameter Measurement Information

3.3V LVDS Output Load AC Test Circuit

Output Skew

Output Rise/Fall Time

RMS Phase Jitter

Bank Skew

Output Duty Cycle/Pulse Width/Period

3.3V ±5%

DD,

DDO_A,

DDA

DDO_B

nQx

nQy

20%

80%

20%

nQA0,

nQB[0:1]

QA0,

QB[0:1]

Phase Noise Mask

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

tsk(b)

nQB0

QB0

nQB1

QB1

nQA0,

nQB[0:1]

QA0,

QB[0:1]

844003I-04 Datasheet

Parameter Measurement Information, continued

Differential Output Voltage Setup Offset Voltage Setup

Applications Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The 844003I-04 provides

separate power supplies to isolate any high switching noise from the

outputs to the internal PLL. V

DD,

DDA,

DDO_A

and V

DDO_B

should

be individually connected to the power supply plane through vias,

and 0.01µF bypass capacitors should be used for each pin. Figure 1

illustrates this for a generic V

pin and also shows that V

DDA

requires that an additional 10 resistor along with a 10F bypass

capacitor be connected to the V

DDA

pin.

Figure 1. Power Supply Filtering

Crystal Input Interface

The 844003I-04 has been characterized with 18pF parallel resonant

crystals. The capacitor values shown in Figure 2 below were

determined using an 18pF parallel resonant crystal and were chosen

to minimize the ppm error.

Figure 2. Crystal Input Interface

DDA

3.3V

10Ω

10µF.01µF

.01µF

XTAL_IN

XTAL_OUT

8pF Parallel Crystal

27pF

844003I-04 Datasheet

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by

one side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 3A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50

 applications,

R1 and R2 can be 100

. This can also be accomplished by removing

R1 and changing R2 to 50. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 3B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC

XTAL_OUT

XTAL_IN

100

Zo = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTA L_ OU T

XTA L_ I N

Zo = 50 ohms

.1uf

LVPECL Driver

Zo = 50 ohms

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844003AKI-04LFT

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844003AKI-04LFT

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