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CY28410ZXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY28410
Document #: 38-07593 Rev. *C Page 4 of 18
Control Registers
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits
.... Data Byte N –8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave – 8 bits
.... NOT Acknowledge
.... Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte – 8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave – 8 bits
38 NOT Acknowledge
39 Stop
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
Byte 0:Control Register 0
Bit @Pup Name Description
7 1 CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6 1 SRC[T/C]6 SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
5 1 SRC[T/C]5 SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4 1 SRC[T/C]4 SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3 1 SRC[T/C]3 SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
2 1 SRC[T/C]2 SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1 1 SRC[T/C]1 SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 1 Reserved Reserved, Set = 1
CY28410
Document #: 38-07593 Rev. *C Page 5 of 18
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6 1 DOT_96T/C DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
5 1 USB_48 USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
4 1 REF REF Output Enable
0 = Disabled, 1 = Enabled
3 0 Reserved Reserved
2 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
0 0 CPUT/C
SRCT/C
PCIF
PCI
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 PCI5 PCI5 Output Enable
0 = Disabled, 1 = Enabled
6 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
5 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
3 1 PCI1 PCI1 Output Enable
0 = Disabled, 1 = Enabled
2 1 PCI0 PCI0 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCIF2 PCIF2 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCIF1 PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit @Pup Name Description
7 0 SRC7 Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
6 0 SRC6 Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
5 0 SRC5 Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4 0 SRC4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
3 0 SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
2 0 SRC2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
CY28410
Document #: 38-07593 Rev. *C Page 6 of 18
1 0 SRC1 Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
0 0 Reserved Reserved, Set = 0
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 Reserved Reserved, Set = 0
6 0 DOT96[T/C] DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
2 1 Reserved Reserved, Set = 1
1 1 Reserved Reserved, Set = 1
0 1 Reserved Reserved, Set = 1
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 SRC[T/C][7:0] SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
6 0 Reserved Reserved, Set = 0
5 0 Reserved Reserved, Set = 0
4 0 Reserved Reserved, Set = 0
3 0 SRC[T/C][7:0] SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 REF/N or Hi-Z Select
1 = REF/N Clock, 0 = Hi-Z
6 0 Test Clock Mode Entry Control
1 = REF/N or Hi-Z mode, 0 = Normal operation
5 0 Reserved Reserved, Set = 0
4 1 REF REF Output Drive Strength
0 = Low, 1 = High
3 1 PCIF, SRC, PCI SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 3: Control Register 3 (continued)
Bit @Pup Name Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY28410ZXC

Mfr. #:
Buy CY28410ZXC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for Intel Lakeport & Grantsdale Chipsets
Lifecycle:
New from this manufacturer.
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