AD8428 Data Sheet
Rev. A | Page 14 of 20
INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8428 applies gain in the
first stage before removing the common-mode voltage in the
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 37) experience a
combination of an amplified differential signal, a common-mode
signal, and a diode drop. This combined signal can be limited by
the voltage supplies even when the individual input and output
signals are not limited. Figure 9 shows the allowable input
common-mode voltage ranges for various output voltages and
supply voltages.
LAYOUT
To ensure optimum performance of the AD8428 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8428 are especially arranged to simplify board
layout and to help minimize parasitic imbalance between the
inputs.
–IN
1
–FIL
2
+FIL
3
+IN
4
+V
S
8
OUT
7
REF
6
–V
S
5
AD8428
TOP VIEW
(Not to Scale)
09731-044
Figure 39. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to
be converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other.
To maintain high CMRR over frequency, the input source
impedance and capacitance of each path should be closely
matched. Additional source resistance in the input paths (for
example, for input protection) should be placed close to the
in-amp inputs to minimize the interaction of the inputs with
parasitic capacitance from the PCB traces.
Parasitic capacitance at the filter pins can also affect CMRR over
frequency. If the board design has a component at the filter pins,
the component should be chosen so that the parasitic capacitance
is as small as possible.
Power Supplies and Grounding
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance. See
the PSRR performance curves in Figure 11 for more information.
Place a 0.1 µF capacitor as close as possible to each supply pin.
Because the length of the bypass capacitor leads is critical at
high frequency, surface-mount capacitors are recommended.
Parasitic inductance in the bypass ground trace works against
the low impedance created by the bypass capacitor.
As shown in Figure 40, a 10 µF capacitor can be used farther
away from the device. For larger value capacitors, which are
intended to be effective at lower frequencies, the current return
path distance is less critical. In most cases, the 10 µF capacitor
can be shared by other precision integrated circuits.
AD8428
+
S
+IN
–IN
LOAD
REF
0.1µF
10µF
0.1µF 10µF
–V
S
OUT
09731-045
Figure 40. Supply Decoupling, REF, and Output Referred to Local Ground
A ground plane layer is helpful to reduce undesired parasitic
inductances and to minimize voltage drops with changes in
current. The area of the current path is directly proportional
to the magnitude of parasitic inductances and, therefore, the
impedance of the path at high frequency. Large changes in
currents in an inductive decoupling path or ground return
create unwanted effects due to the coupling of such changes
into the amplifier inputs.
Because load currents flow from the supplies, the load should
be connected at the same physical location as the bypass capac-
itor grounds.
Reference Pin
The output voltage of the AD8428 is developed with respect to
the potential on the reference terminal. Ensure that REF is tied
to the appropriate local ground.
