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April 2018 DocID031781 Rev 1 1/12
EVALSTGAP2SCM
Demonstration board for STGAP2SCM isolated 4 A single
gate driver
Data brief
Features
High voltage rail up to 1700 V
Driver current capability:
– 4 A source/sink at 25 °C
Separate sink and source for simplified gate
driving configuration (STGAP2SM)
4 A Miller clamp (STGAP2SCM)
Short propagation delay: 100 ns
UVLO function
Gate driving voltage up to 26 V
Negative gate driving
On-board isolated DC-DC converters to supply
gate drivers, fed by VAUX = 5 V
VDD logic supply local 3.3 V or VAUX
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Easy jumper selection of driving voltage
configuration:
– +15/0 V; +15/-3 V; +19/0 V; +19/-3 V
Temperature shutdown protection
Description
The STGAP2SCM is an isolated single gate
driver.
The gate driver is characterized by 4 A current
capability and rail-to-rail outputs, making the
device suitable also for high power inverter
applications such as motor drivers in industrial
applications equipped with MOSFET/IGBT/SiC
power switch.
Two different variants are available: one with
separated source and sink outputs, the other with
single output pin and a dedicated pin for Miller
clamp function. The EVALSTGAP2S is suitable
for both output configuration variants.
The device integrates protection functions: UVLO
and thermal shutdown are included to simplify the
design of high reliability systems. Dual input pins
allow choosing the control signal polarity and also
implementing HW interlocking protection in order
to avoid cross-conduction in case of controller
malfunction.
The device allows the implementation of negative
gate driving, and the on-board isolated DC-DC
converters allow working with optimized driving
voltage for MOSFET/IGBT or SiC.
The EVALSTGAP2S board allows evaluating all
the STGAP2SCM features while driving a half-
bridge power stage with voltage rating up to
1700 V in TO-220 or TO-247 package.
The board facilitates the selection and
modification of the values of relevant external
components in order to ease driver's performance
evaluation under different applicative conditions
and fine pre-tuning of final application
components.
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