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87001BGI-01LFT

P1-P3P4-P6P7-P9P10-P12P13-P14
DATA SHEET
ICS87001BGI-01 REVISION A JANUARY 23, 2013 1 ©2013 Integrated Device Technology, Inc.
LVCMOS/LVTTL Clock Divider ICS87001I-01
General Description
The ICS87001I-01 is a low skew, ÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷8, ÷16
LVCMOS/LVTTL Clock Divider. The ICS87001I-01 has selectable
clock inputs that accept single ended input levels. Output enable pin
controls whether the output is in the active or high impedance state.
The ICS87001I-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001I-01 ideal for those applications demanding well defined
performance and repeatability.
Features
• One LVCMOS / LVTTL output
• Selectable LVCMOS / LVTTL clock inputs
• Maximum output frequency: 250MHz
• Part-to-part skew: 135ps (typical)
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
N Output Divider
N2:N0
0 0 0 ÷1 (default)
001 ÷2
010 ÷3
011 ÷4
100 ÷5
101 ÷6
110 ÷8
111 ÷16
0
1
3
Q
OE
N2:N0
CLK1
CLK0
CLK_SEL
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N0
N1
N2
CLK1
CLK_SEL
CLK0
V
DD
OE
V
DDO
nc
Q
nc
GND
nc
nc
GND
Pin Assignment
Block Diagram
ICS87001I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
ICS87001BGI-01 REVISION A JANUARY 23, 2013 2 ©2013 Integrated Device Technology, Inc.
ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Programmable Output Divider Function Table
Number Name Type Description
1 OE Input Pullup
Output enable. When LOW, output is in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
2V
DD
Power Power supply pin.
3, 5 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
4 CLK_SEL Input Pulldown
Input clock selection. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
6, 7, 8 N2, N1, N0 Input Pulldown Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3.
9, 12 GND Power Power supply ground.
10, 11, 13, 15 nc Unused No connect.
14 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels.
16 V
DDO
Power Output supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation
Capacitance
V
DDO
= 3.465V 6 pF
V
DDO
= 2.625V 5 pF
V
DDO
= 1.95V 5 pF
R
OUT
Output Impedance
V
DDO
= 3.3V±5% 17
V
DDO
= 2.5V±5% 20
V
DDO
= 1.8V±0.15V 28
Inputs
N Divider Value Maximum Output Frequency (MHz)N2 N1 N0
0 0 0 ÷1 (default) 250
0 0 1 ÷2 125
0 1 0 ÷3 83.333
0 1 1 ÷4 62.5
1 0 0 ÷5 50
1 0 1 ÷6 41.667
1 1 0 ÷8 31.25
1 1 1 ÷16 15.625
ICS87001BGI-01 REVISION A JANUARY 23, 2013 3 ©2013 Integrated Device Technology, Inc.
ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
=V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 4B. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 4C. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
=1.8V ± 0.15V, T
A
= -40°C to 85°C
Table 4D. Power Supply DC Characteristics, V
DD
=V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
100.3C/W (0 mps)
Storage Temperature, T
STG
-65Cto150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 55 mA
I
DDO
Output Supply Current No Load 5 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 55 mA
I
DDO
Output Supply Current No Load 5 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 1.65 1.8 1.95 V
I
DD
Power Supply Current 55 mA
I
DDO
Output Supply Current No Load 5 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 2.375 2.5 2.625 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 55 mA
I
DDO
Output Supply Current No Load 5 mA
P1-P3P4-P6P7-P9P10-P12P13-P14

87001BGI-01LFT

Mfr. #:
Buy 87001BGI-01LFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution LVCMOS/LVTTL Clock Divider
Lifecycle:
New from this manufacturer.
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